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Pertemuan 4 Physical Structure

Pertemuan 4 Physical Structure. Matakuliah : H0362/Very Large Scale Integrated Circuits Tahun : 2005 Versi : versi/01. Learning Outcomes. Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menunjukkan proses physical design pada teknologi VLSI. Layer M1. Layer M1. insulator.

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Pertemuan 4 Physical Structure

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  1. Pertemuan 4Physical Structure Matakuliah : H0362/Very Large Scale Integrated Circuits Tahun : 2005 Versi : versi/01

  2. Learning Outcomes Pada Akhir pertemuan ini, diharapkan mahasiswa akan dapat menunjukkan proses physical design pada teknologi VLSI.

  3. Layer M1 Layer M1 insulator Bentuk fisik 2 materi layers terpisah Layer M1 Layer M1 Substrate insulator Substrate Tampak atas Tampak samping IC Layers

  4. Layer M1 Bentuk fisik Layer M2 insulator Layer M1 insulator Layer M2 Tampak samping Tampak atas y x l t w l 1 square x y Substrate Cross section area A w Sheet resistance contributions Geometry conducting line IC Layers

  5. w Pengaruh capacitancy ox l Tox Geometry untuk menghitung line capacitancy Substrate Next logik gate Signal source V(t) Vs(t) V(t) Vs(t) + + Vs(t) V(t) Cline - t  Response tegangan Model rangkaian IC Layers

  6. Gate Drain Source Gate layer nFET symbol Drain layer Source layer No connection Conduction layer nFET layers G = 0 G = 1 Open switch Closed switch MOSFET

  7. Gate Gate Gate Gate oxide Source Source Silicon dioxide insulator Source Drain Drain L w Drain substrate L Silicon wafer Tampak samping Tampak atas w MOSFET Layers

  8. MOSFET Silicon cristal Konduksi di silicon Elektron ( -q) Hole ( +q) Pembentukan pasangan elektron – hole pada silicon I = 0 p p p n n n Reverese current pn junction Forward current

  9. Source Gate Source Gate Drain Drain Metal n+ n+ p+ p+ n-well p p MOSFET nFET dan pFET nFET pFET

  10. Controlling current flow nFET: Open switch 0 V w n+ n+ n+ n+ No electron p L Closed switch VG positip + w n+ n+ n+ n+ electron p Kanal elektron MOSFET

  11. Controlling current flow pFET: Open switch + w p+ p+ p+ p+ No hole n L Closed switch VG negatip - w p+ p+ p+ p+ Hole (+q) n Kanal hole MOSFET

  12. Struktur layers nFET pFET nFET pFET FOX Gate p+ n+ n+ p+ p+ n+ n+ p+ Gate oxide p-substrate n-well Tampak samping nFET pFET nFET pFET n+ n+ n+ n+ p+ p+ p+ p+ n-well Tampak atas CMOS Layers

  13. Ox3 Metal 2 Ox2 Metal 1 Gate contact Ox1 Gate Active contact Metal 1 n+ n+ n+ n+ Metal 2 p-substrate Metal 1 FET Active contact Metal 1 Contoh interkoneksi layout CMOS Layers Metal interconnection

  14. A B A B n+ n+ n+ n+ n+ n+ Substrate A B C y x skematik FET Arrays Serial Connection A B n+ n+ n+ Tampak samping skematik Surface patern A B C Poly (gate) y n+ / p+ Metal Contact x Surface patern

  15. x Paralel Connection B A x A B y Skematik Surface patern y Poly (gate) x x n+ / p+ Metal Contact B A y y Skematik Surface patern FET Arrays

  16. Vdd NAND gate using gate isolation Vdd A B PMOS B A Out Out NMOS Gnd Can in principle be used by adjacent cell Gnd Gate Arrays

  17. Gate Arrays Check and recheck

  18. RESUME • IC Layers: bentuk dan pengaruh kapasitansi. • MOSFET: Simbol, layers, nFET, pFET, controlling current. • CMOS layers: structure, metal connection. • FET and Gate arrays.

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