Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving

1. Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving Zhiyuan He 1 , Zebo Peng 1 , Petru Eles 1Paul Rosinger 2 , Bashir M. Al-Hashimi 2 1 Linköping University, Sweden2 University of Southampton, U.K.

2. Core-based System-on-Chip • Integration of pre-designed and pre-verified cores in a single chip • Advantages • Reduced design complexity • Lower cost • Shorter time-to-market • Challenges to testing • Large quantities of test data, long test time • High power consumption, high temperature • Need efficient test approach

3. Source: Fred Pollack (Intel Corp.), Micro32, “New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies” Increasing Power Density High power density  high temperature on chip!

4. Thermal Issue in SoC Test • Higher power dissipation during test than in normal operations [Pouya, ITC’00] • High temperature during test • Slow down transistors • Large RC delay • High leakage • Shorter lifetime • Permanent damage • Require temperature-aware test techniques

5. Contribution • An SoC test scheduling technique that • Minimizes test application time • Prevents over-heating during test • Utilizing test set partitioning and interleaving

6. Outline • Basic Test Architecture • Test Set Partitioning and Interleaving • Problem Formulation • Constraint Logic Programming (CLP) • Experimental Results and Conclusions

7. Basic Test Architecture • Tester • Test controller • Tester memory • On-chip or external • Test bus (single) • Bandwidth limit • Dedicated TAM wires connecting cores to the test bus

8. Test Set Partitioning

9. Test Set Interleaving Test for Core 1 Test for Core 2

10. The Basic Strategy Generate an initial partitioning scheme(thermal-safe, min number of partitions)using temperature simulation (HotSpot) Generate alternative partitioning schemes w.r.t. the number of partitions Generate the optimal test schedule constrained by a bus bandwidth limit

11. Assumption • A test set is partitioned into test sequences with equal lengths, except the first one • To simplify the test controller • To reduce design space

12. A Motivational Example

13. Test Time Minimization Problem • Input • Test architecture • Test sets for all cores • Test bus bandwidth limit Bmax • Temperature upper limit TMi,max for each core Ci • Output • The optimized test schedule • Objective • Minimize the total test time TTT • Subject to • Total amount of bus bandwidth utilization B < Bmax • Temperature of each core TMi < TMi,max

14. Constraint Logic Programming • Define relationships or constraints by using logic programming language • Provide solvers to find optimal solutions • Exhaustive search • Branch and bound • CHIP • Developed by COSYTEC • Uses Prolog • Integrated solvers

15. Experimental Results

16. Conclusions • An exact approach to minimize total test time for SoC test under a temperature upper limit and bus bandwidth limit • Proposed test set partitioning and interleaving techniques • Optimal solution obtained by using constraint logic programming

17. Thank you!