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SAT-Based Static Assertion Checking

Definition: Given a Boolean formula , decide if there is an assignment to the variables in such that evaluates to true . Example: Solution: evaluates to true (is satisfied) if = 0, = 1, = 1. R-Verify ™ : Deep Checking of Embedded Code Reservoir Labs, Inc.

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SAT-Based Static Assertion Checking

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  1. Definition: Given a Boolean formula , decide if there is an assignment to the variables in such that evaluates to true. Example: Solution: evaluates to true (is satisfied) if = 0, = 1, = 1. R-Verify™: Deep Checking of Embedded CodeReservoir Labs, Inc. R-Verify Design Deep Bit-Level Checking SAT-Based Static Assertion Checking • How does it work? • Model the program (P) and the verification conditions (Q) using constraints • 2. Use Alef SAT solver to look for a solution to: P ^ ¬Q • 3. Decode an Alef solution into a counter-example • R-Verify is built on three core Reservoir Labs technologies: • R-Stream™ – a high-level compiler which contains a state-of-the-art framework that permits a wide-range of program analyses • Salt™ – a constraint translator which efficiently generates optimized constraint systems from high-level program descriptions • Alef™ – a multiprocessor Boolean satisfiability (SAT) solver which contains novel algorithms that allow it to take advantage of HPC hardware Application to VSIPL Development & Verification Cycle “R-Verify can quickly and efficiently find deep software errors that are invisible to superficial abstraction-based analysis. These types of errors are common in low-level embedded code and can easily go undetected during the normal software testing process. These undiscovered errors can be fatal in deployed software.” The Satisfiability Problem R-Verify plugs-in to existing IDEs such as Eclipse via an 8-step cycle: • Normal IDE Source Development • R-Stream compiler builds an internal representation of the code • IR and specification are translated to Salt constraints • Salt tool translates the combined constraints to annotated CNF • Alef searches for an execution that violates the specification • Violation is returned to R-Stream • Violation is reflected as an error path in the R-Stream IR • Error path in the R-Stream IR is reflected back to the IDE • We are currently applying R-Verify to: • Pre- and post-condition checking including all of the above VSIPL rules • Memory safety of embedded device drivers, interrupt handlers, and VSIPL “admitted” blocks • Numerical precision of arithmetic pipelines with an emphasis on VSIPL pipeline implementations

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