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CS4290/CS6290/ECE4100/ECE6100

CS4290/CS6290/ECE4100/ECE6100. Fall 2012 Prof. Hyesoon Kim . Lab #2: Memory Systems . 3 Components Complete dcache Complete MSHR handling Complete DRAM handling Sufficiently longer than Lab #1, so please start early. . Memory System. dcache. EXE_latch. MEM_latch. MSHR.

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CS4290/CS6290/ECE4100/ECE6100

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  1. CS4290/CS6290/ECE4100/ECE6100 Fall 2012 Prof. Hyesoon Kim

  2. Lab #2: Memory Systems • 3 Components • Complete dcache • Complete MSHR handling • Complete DRAM handling • Sufficiently longer than Lab #1, so please start early.

  3. Memory System dcache EXE_latch MEM_latch MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  4. Stall-at-Issue vs Stall-at-Use • Stall when there is a cache miss • Stall when a data is not ready

  5. Examples • MSHR size is 2, 16B cache block size • DARM row buffer size is 4KB.

  6. Memory System Inst1: LD R1 0x0010 inst2: LD R2 0x0020 dcache LD R1, 0x010 EXE_latch MEM_latch MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 4 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  7. Memory System Inst1: LD R1 0x0010 inst2: LD R2 0x0020 dcache Miss! EXE_latch MEM_latch LD R1, 0x010 MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 7 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  8. Memory System Inst1: LD R1 0x0010 inst2: LD R2 0x0020 dcache LD R1, 0x020 EXE_latch MEM_latch LD R1, 0x010 MSHR LD 0x010 DRAM_IN_QUEUE DRAM_OUT_QUEUE Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 8 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  9. Memory System Inst1: LD R1 0x0010 inst2: LD R2 0x0020 dcache LD R1, 0x020 EXE_latch MEM_latch LD R1, 0x010 MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE LD 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 9 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  10. Memory System Inst1: LD R1 0x0010 inst2: LD R2 0x0020 dcache LD R1, 0x020 EXE_latch MEM_latch LD R1, 0x010 MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE LD 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles Ready_cycle = 10+100 10 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  11. Memory System Inst1: LD R1 0x0010 inst2: LD R2 0x0020 dcache Miss! EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = 10+100 LD 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 11 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  12. Memory System Inst1: LD R1 0x0010 inst2: LD R2 0x0020 dcache Miss! EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE LD 0x020 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles Ready_cycle = 10+100 LD 0x010 12 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  13. Memory System Inst1: LD R1 0x0010 inst2: LD R2 0x0020 dcache Miss! EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE LD 0x020 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles Ready_cycle = 10+100 LD 0x010 13 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  14. Memory System Inst1: LD R1 0x0010 inst2: LD R2 0x0020 dcache Miss! EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 0x010 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = 111+40 LD 0x020 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 111 Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  15. Memory System Inst1: LD R1 0x0010 inst2: LD R2 0x0020 dcache 0x010 LD R1, 0x010 EXE_latch MEM_latch MSHR LD R1, 0x020 0x010 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = 111+40 LD 0x020 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 112 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  16. Memory System Inst1: LD R1 0x0010 inst2: LD R2 0x0020 dcache Retire!! LD R1, 0x010 EXE_latch MEM_latch MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = 111+40 LD 0x020 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 113 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  17. Memory System Inst1: LD R1 0x0010 inst2: LD R2 0x0020 dcache EXE_latch MEM_latch MSHR LD R1, 0x020 LD 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 152 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  18. Memory System Inst1: LD R1 0x0010 inst2: LD R2 0x0020 dcache LD 0x020 LD R1, 0x020 EXE_latch MEM_latch MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE LD 0x020 153 Dcache access latency: 4 cycles Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  19. Memory System Inst1: LD R1 0x0010 inst2: LD R2 0x0020 dcache Retire!! LD R1, 0x020 EXE_latch MEM_latch MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE 154 Dcache access latency: 4 cycles Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  20. Inst1: LD R1 0x0010: miss inst2: LD R2 0x0020: miss Inst3: LD R3 0x0040: hit Case #2:Hit under misses dcache Miss! EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = 10+100 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles LD 0x010 11 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  21. Inst1: LD R1 0x0010 inst2: LD R2 0x0020 Inst3: LD R3 0x0040 Case #2:Hit under misses dcache LD R1, 0x040 EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = ?? LD 0x020 Ready_cycle = 10+100 LD 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 12 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  22. Inst1: LD R1 0x0010 inst2: LD R2 0x0020 Inst3: LD R3 0x0040 Case #2:Hit under misses LD R1, 0x040 dcache Hit! EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = ?? LD 0x020 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles Ready_cycle = 10+100 LD 0x010 15 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  23. Inst1: LD R1 0x0010 inst2: LD R2 0x0020 Inst3: LD R3 0x0040 Case #2:Hit under misses dcache Retire!! LD R1, 0x040 EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = ?? LD 0x020 Ready_cycle = 10+100 LD 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 16 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  24. Inst1: LD R1 0x0010 miss inst2: LD R2 0x0020 miss Inst3: LD R3 0x0040 miss Case #3: MSHR Full dcache Miss! EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = 10+100 LD 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 11 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  25. Inst1: LD R1 0x0010 miss inst2: LD R2 0x0020 miss Inst3: LD R3 0x0040 miss Case #3: MSHR Full dcache LD R1, 0x040 EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = ?? LD 0x020 Ready_cycle = 10+100 LD 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 12 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  26. Inst1: LD R1 0x0010 miss inst2: LD R2 0x0020 miss Inst3: LD R3 0x0040 miss Case #3: MSHR Full dcache No SPACE!!! LD R1, 0x040 Miss! EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = ?? LD 0x020 Ready_cycle = 10+100 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles LD 0x010 15 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  27. Inst1: LD R1 0x0010 miss inst2: LD R2 0x0020 miss Inst3: LD R3 0x0040 miss Case #3: MSHR Full dcache STALL!!! LD R1, 0x040 Miss! EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = ?? LD 0x020 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles Ready_cycle = 10+100 LD 0x010 15 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  28. Inst1: LD R1 0x0010 miss inst2: LD R2 0x0020 miss Inst3: LD R3 0x0040 miss Case #3: MSHR Full dcache STALL!!! LD R1, 0x040 EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = ?? LD 0x020 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles Ready_cycle = 10+100 LD 0x010 16 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  29. Inst1: LD R1 0x0010 miss inst2: LD R2 0x0020 miss Inst3: LD R3 0x0040 miss Case #3: MSHR Full dcache STALL!!! LD R1, 0x040 EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = ?? LD 0x020 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles Ready_cycle = 10+100 LD 0x010 17 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  30. Inst1: LD R1 0x0010 miss inst2: LD R2 0x0020 miss Inst3: LD R3 0x0040 miss Case #3: MSHR Full dcache STALL!!! LD R1, 0x040 EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 0x010 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = 111+40 LD 0x020 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 111 Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  31. Inst1: LD R1 0x0010 miss inst2: LD R2 0x0020 miss Inst3: LD R3 0x0040 miss Case #3: MSHR Full dcache 0x010 inst 4 LD R1, 0x010 EXE_latch MEM_latch LD R1, 0x040 MSHR LD R1, 0x020 0x010 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = 111+40 LD 0x020 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 112 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  32. Inst1: LD R1 0x0010 miss inst2: LD R2 0x0020 miss Inst3: LD R3 0x0040 miss Case #3: MSHR Full dcache Retire!! inst 4 LD R1, 0x010 EXE_latch MEM_latch LD R1, 0x040 MSHR LD R1, 0x020 LD 0x040 DRAM_IN_QUEUE DRAM_OUT_QUEUE Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles Ready_cycle = 111+40 LD 0x020 113 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  33. Inst1: LD R1 0x0010 miss inst2: LD R2 0x0020 miss Inst3: LD R3 0x0040 miss Case #3: MSHR Full dcache inst 4 EXE_latch MEM_latch LD R1, 0x040 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = ? LD 0x040 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles Ready_cycle = 111+40 LD 0x020 114 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  34. Inst1: LD R1 0x0010: miss inst2: LD R2 0x0020: miss Inst3: LD R3 0x0011 Case #4:MSHR Hit dcache Miss! EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = 10+100 LD 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 11 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  35. Inst1: LD R1 0x0010 inst2: LD R2 0x0020 Inst3: LD R3 0x0011 Case #4:MSHR Hit dcache LD R1, 0x011 EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = ?? LD 0x020 Ready_cycle = 10+100 LD 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 12 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  36. Inst1: LD R1 0x0010 inst2: LD R2 0x0020 Inst3: LD R3 0x0011 Case #4:MSHR Hit dcache LD R1, 0x11 Miss! EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = ?? LD 0x020 Ready_cycle = 10+100 LD 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 15 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  37. Inst1: LD R1 0x0010 inst2: LD R2 0x0020 Inst3: LD R3 0x0011 Case #4:MSHR Hit dcache Piggyback Miss! LD R1, 0x11 EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = ?? LD 0x020 Ready_cycle = 10+100 LD 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 15 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  38. Inst1: LD R1 0x0010 inst2: LD R2 0x0020 Inst3: LD R3 0x0011 Case #4:MSHR Hit dcache Miss! LD R1, 0x11 EXE_latch MEM_latch LD R1, 0x010 MSHR LD R1, 0x020 0x010 DRAM_IN_QUEUE DRAM_OUT_QUEUE LD 0x020 Ready_cycle = 111+40 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 111 Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  39. Inst1: LD R1 0x0010 inst2: LD R2 0x0020 Inst3: LD R3 0x0011 Case #4:MSHR Hit dcache 0x010 LD R1, 0x11 LD R1, 0x010 EXE_latch MEM_latch MSHR LD R1, 0x020 0x010 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = 111+40 LD 0x020 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 112 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  40. Inst1: LD R1 0x0010 inst2: LD R2 0x0020 Inst3: LD R3 0x0011 Case #4:MSHR Hit dcache Retire!! LD R1, 0x11 LD R1, 0x010 EXE_latch MEM_latch MSHR LD R1, 0x020 DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = 111+40 LD 0x020 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 113 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  41. Inst1: ST R1 0x0010 inst2: LD R2 0x0010 Case #5: Store-Load dcache ST 0x010 EXE_latch MEM_latch MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 4 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  42. Inst1: ST R1 0x0010 inst2: LD R2 0x0010 Case #5: Store-Load dcache STR1, 0x010 MSHR has an empty req ops pointer and the op pointer is moved to MEM latch Miss! EXE_latch MEM_latch STR1, 0x010 MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 7 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  43. Inst1: ST R1 0x0010 inst2: LD R2 0x0010 Case #5: Store-Load dcache LD R1, 0x010 STR1, 0x010 EXE_latch MEM_latch ST 0x010 MSHR ST 0x010 DRAM_IN_QUEUE DRAM_OUT_QUEUE Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 8 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  44. Inst1: ST R1 0x0010 inst2: LD R2 0x0010 Case #5: Store-Load dcache LD R1, 0x010 EXE_latch MEM_latch ST 0x010 MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles ST 0x010 9 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  45. Inst1: ST R1 0x0010 inst2: LD R2 0x0010 Case #5: Store-Load dcache LD R1, 0x010 EXE_latch MEM_latch ST 0x010 MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = 10+100 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles ST 0x010 10 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  46. Inst1: ST R1 0x0010 inst2: LD R2 0x0010 Case #5: Store-Load dcache MSHR Hit ! Store-load forwarding!!! Miss! LD R1, 0x010 EXE_latch MEM_latch ST 0x010 MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = 10+100 ST 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 11 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  47. Inst1: ST R1 0x0010 inst2: LD R2 0x0010 Case #5: Store-Load dcache Hit! LD R1, 0x010 EXE_latch MEM_latch ST 0x010 MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle=10+100 ST 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 11 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  48. Inst1: ST R1 0x0010 inst2: LD R2 0x0010 Case #5: Store-Load dcache Retire!! LD R1, 0x010 EXE_latch MEM_latch ST 0x010 MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE Ready_cycle = 10+100 ST 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 12 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  49. Inst1: ST R1 0x0010 inst2: LD R2 0x0010 Case #5: Store-Load dcache EXE_latch MEM_latch ST 0x010 MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE ST 0x010 Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 111 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

  50. Inst1: ST R1 0x0010 inst2: LD R2 0x0010 Case #5: Store-Load dcache Cache block:0x010 EXE_latch MEM_latch MSHR DRAM_IN_QUEUE DRAM_OUT_QUEUE Dcache access latency: 4 cycles DRAM Row buffer miss: 100 cycles DRAM Row buffer hit: 40 cycles 112 Dcache access latency: 3 cycle Cycle: DRAM BANK DRAM BANK DRAM BANK DRAM BANK ROW ID ROW ROW ROW ROW

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