TOPIC : Types of fault simulation

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# TOPIC : Types of fault simulation - PowerPoint PPT Presentation

TOPIC : Types of fault simulation. UNIT 2 : Fault modeling. Module 2.4 Fault Simulation. Fault Simulation Set-up. Fault Simulation types. In large circuits, The number of faults are large Time taken to test the circuit will also be large.

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### TOPIC : Types of fault simulation

UNIT 2 : Fault modeling

Module 2.4 Fault Simulation

Fault Simulation types

In large circuits,

• The number of faults are large
• Time taken to test the circuit will also be large.
• So we do different types of type of simulation to save time and memory.
• We will analyze different types of fault simulation techniques for stuck at fault.
Different types of fault Simulation
• Serial fault simulation
• Parallel fault simulation
• Deductive fault simulation
• Concurrent fault simulation
Serial fault Simulation
• It consists of transforming the model of the fault-free circuit N so that it models the circuit Nf created by the fault f.
• Then Nf is simulated.
• The entire process is repeated for each fault of interest. Thus faults are simulated one at a time.
• No special fault simulator is required, as Nf is simulated by a fault-free simulator.
• It can handle any type of fault, provided that the model of Nf is known.
• the serial method is impractical for simulating a large number of faults because it would consume an excessive amount of CPU time.
Parallel fault Simulation
• In this the good circuit and a fixed number(say W), of faulty circuits are simultaneously simulated.
• The values of a signal in the good circuit and the values of the corresponding signals in the W faulty circuits are placed in a register.
• Then these values are all compared with the value of good circuit to check for fault using some logic(e.g. XOR).
Parallel fault Simulation Example
• For example, if we use 2-valued logic and a 32-bit word, then W=31
• In parallel fault simulation several faulty circuits can be simulated in parallel.
• These types of evaluations are convenient for evaluating functional elements, such as memories and counters.
• An event, a value change, of a single fault or fault-free circuit leads to the computation of the entire word.
Deductive fault simulation
• The deductive technique simulates the good circuit and deduces the behavior of all faulty circuits.
• This method utilizes a dynamic data

structure.

• It comprises of two steps:

a) Fault-free circuit simulation is performed for the given vector.

b) The value implied by the vector at every line in each faulty circuit is deduced (using set theoretic rules).

• Fault lists can be stored as linked lists, sequential tables, or characteristic vectors.
Deductive fault simulation Example
• In parallel simulation the word associated with a line i stores the value of i in every faulty circuit..
• During simulation, however, the value of i in most faulty circuits is the same as in the good circuit.
• This waste is avoided in deductive simulation by keeping only the bit positions (used as fault names) that are different from the good value.

Here line 4 and 7 are faulty, so in deductive fault simulation a list of Li={4,7} is made while, in parallel fault simulation a register is filled with all the faulty circuits

Concurrent fault simulation
• Most of the time during simulation, most of the values in most of the faulty circuits agree with the corresponding values in the good circuit.
• The fault-free version of the circuit, and each of its faulty versions, are concurrently simulated for a given vector.

• Simulates the good circuit N.

• For every faulty circuit Nf, simulate only those elements in Nf that are different from the corresponding ones in N.

Concurrent fault simulation Example
• Data structure used:

– Concurrent fault list, in which entries are of the form:

< fault, input_values, output_value >

Critical Path Tracing
• A line l is critical w.r.t. a pattern t iff t detects the fault l/v.
• Paths of critical lines are critical paths.
• A gate input i is sensitive if complementing the value of I changes the value of the gate output.
• A gate input i is critical w.r.t. a pattern t if the gate output is critical and i is sensitive w.r.t. t.
• Backtracking : In a fanout-free circuit, the criticality of all lines can be determined by backward traversing the successive sensitive gate inputs from POs, in linear time.