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Sune Fallgaard Nielsen Informatics and Mathematical Modelling Technical University of Denmark Richard Petersens Plads, Building 322 DK2800 Lyngby, Denmark. Path-Based Scheduling. Overview. Motivation Introduction – Prior work / new paradigm Defining problem and model constraints

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Presentation Transcript
path based scheduling
Sune Fallgaard Nielsen

Informatics and Mathematical Modelling

Technical University of Denmark

Richard Petersens Plads, Building 322

DK2800 Lyngby, Denmark

Path-Based Scheduling

overview
Overview
  • Motivation
  • Introduction – Prior work / new paradigm
  • Defining problem and model constraints
  • Solution:
    • AFAP Scheduling
    • Algorithm
    • The scheduling steps using AFAP
  • Results
  • Conclussion

[M-1] High Level Synthesis

motivation
Motivation

Derive a synthesis tool which:

  • Minimizes the number of control steps
  • Takes constraints into account
  • Considers loops and conditional branches

( which no prior work has done )

[M-1] High Level Synthesis

introduction
Introduction
  • Prior work: scheduling <- minimize cost function
  • Cost function:

- Fixed hardware (uP): Number of states

- Hardware syntheses: Number of states + hardware

  • Scheduling:

Minimizing the cost function by moving operations around

  • Optimal solution:

- Optimal schedule emphasizing concurrency

- Force directed serialization + moving mobile operations

[M-1] High Level Synthesis

introduction problem
Introduction / Problem
  • Path-Based Scheduling for Synthesis:
  • Forget cost functions!
  • Instead: Emphasize on conditional branches, loops
  • Minimize number of control steps

- taking constraints into account ( main problem )

  • Main problem: Gain advantages from looking at branches

[M-1] High Level Synthesis

constraints
Constraints
  • Internal constraints:
  • Units can only receive and output values once per cycle
  • With single phase clock this implies single use per cycle
  • External constraints:
  • Amount of hardware available:
  • Area, units etc.
  • Timing constraints

[M-1] High Level Synthesis

afap scheduling
AFAP scheduling

AFAP ( As Fast As Possible )

Basic idea:

  • Control-flow directed graph- Nodes (ops.). Edges (precedence relations).
  • Longest path: Max number of operations. Cycles only traversed once (%loop unfolding)
  • Scheduling: Put as many operations into one control step as possible in all possible paths.

Goal: Finite State Machine to implement control

[M-1] High Level Synthesis

afap scheduling for a single path
AFAP Scheduling for a single path

AFAP Sch. for a single path ( no loops/branches )

  • Longest path is computed
  • For every path constraints are computed (variables, IOs, func. Units, max delay) and “Cut”s are lain in according to constraints
  • Interval graph is formed with cliques (complete subgraph of all poss. edges)
  • Cuts an cliques are stored for later processing

[M-1] High Level Synthesis

afap scheduling for a single path9
AFAP Scheduling for a single path

[M-1] High Level Synthesis

afap the algorithm
AFAP – The algorithm

The four steps to Nirvana ( or something ):

  • Transform the control flow graph into a directed acyclic graph (DAG)
  • All paths in the DAG are scheduled AFAP
  • Schedules are overlapped in a way to minimize the number of control steps
  • The finite state machine is built.

[M-1] High Level Synthesis

afap example
AFAP – Example

[M-1] High Level Synthesis

building finite state machine
Building finite state machine

Trivial finite state machine design:

  • Overlapping of intervals to form states (same cut -> same state)
  • Construct state transitions (figure out control signals for each state)
  • Construct state transition conditions (rules for looping, waiting etc)

[M-1] High Level Synthesis

results
Results
  • Comparison is difficult since goals are different.
  • Different compiler machines used

[M-1] High Level Synthesis

conclusion good things bad things
Conclusion: Good things / bad things

Good things:

Real life examples

Good results

Bad things:

No support for secondary hardware constraints

- like busses, registers, ports etc.

No smart loop unfolding capabilities

No pipeline scheduling capabilities

No instruction execution reordering supported

[M-1] High Level Synthesis

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