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Design Patterns

Design Patterns. University of Waterloo E&CE 427 2001 Fall Lec-03. Storage: Dual-Port Memory Array. Can read from two addresses at same time Can write to one address at a time Area: 1.5 - 2x that of single-port memory. write_enA. 0. addrA. 1. data_inA. data_outA. 2. addrB.

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Design Patterns

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  1. Design Patterns University of Waterloo E&CE 427 2001 Fall Lec-03

  2. Storage: Dual-Port Memory Array • Can read from two addresses at same time • Can write to one address at a time • Area: 1.5 - 2x that of single-port memory write_enA 0 addrA 1 data_inA data_outA 2 addrB data_outB 3

  3. Concurrent State Machines • Decompose a state machine into several machines operating concurrently (in parallel) • Common decomposition is based on output signals • Simplifies next-state equations • Can increase performance and reduce area

  4. Datapath Design and Optimization University of Waterloo E&CE 427 2001 Fall Lec-04

  5. Design Comparison inputs 2 3 1 adders 2 1 outputs 1 2 3 registers clock speed f 0.5f latency 6 4 a b c d e f a b c + + d e + + + + f + + + + z z

  6. From Dataflow to Hardware • Clean up the drawing, add the state machine in1 in2 in3 r3 a b c r1 r2 + r3 d e r2 + + r1 + + f + r1 r2 + r3 z out1

  7. Datapath + Storage + Control • The three main classes of hardware datapath storage + control +

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