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Digital Integrated Circuits A Design Perspective

Digital Integrated Circuits A Design Perspective. The Inverter. July 30, 2002. V. DD. CMOS Inverter. N Well. PMOS. 2 l. Contacts. Out. In. Metal 1. Polysilicon. NMOS. GND. Two Inverters. Share power and ground Abut cells. Connect in Metal. t. = f(R. .C. ). pHL. on. L.

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Digital Integrated Circuits A Design Perspective

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  1. Digital Integrated CircuitsA Design Perspective The Inverter July 30, 2002

  2. V DD CMOS Inverter N Well PMOS 2l Contacts Out In Metal 1 Polysilicon NMOS GND

  3. Two Inverters Share power and ground Abut cells Connect in Metal

  4. t = f(R .C ) pHL on L = 0.69 R C on L CMOS Inverter: Transient Response V V DD DD R p V out V out C L C L R n V 0 V V 5 5 in DD in (a) Low-to-high (b) High-to-low

  5. Voltage TransferCharacteristic

  6. CMOS Inverter Load Characteristics

  7. CMOS Inverter VTC

  8. 1.8 1.7 1.6 1.5 1.4 (V) 1.3 M V 1.2 1.1 1 0.9 0.8 0 1 10 10 /W W p n Switching Threshold as a function of Transistor Ratio

  9. V out V OH V M V in V OL V V IL IH Determining VIH and VIL A simplified approach

  10. Gain as a function of VDD

  11. 2.5 2 Good PMOS Bad NMOS 1.5 Nominal (V) out Good NMOS Bad PMOS V 1 0.5 0 0 0.5 1 1.5 2 2.5 V (V) in Impact of Process Variations

  12. Propagation Delay

  13. CMOS Inverter Propagation Delay

  14. Transient Response ? tp = 0.69 CL (Reqn+Reqp)/2 tpHL tpLH

  15. Design for Performance • Keep capacitances small: Cload, Cgate, Cdiff • Increase transistor sizes: W/L • watch out for self-loading! • Increase VDD (????)

  16. Delay as a function of VDD

  17. Device Sizing (for fixed load) Self-loading effect: Intrinsic capacitances dominate

  18. NMOS/PMOS ratio tpHL tpLH tp b = Wp/Wn

  19. Inverter Sizing

  20. Inverter Chain In Out CL • If CL is given: • How many stages are needed to minimize the delay? • How to size the inverters? • May need some additional constraints.

  21. Inverter Delay • Minimum length devices, L=0.25mm • Assume that for WP = 2WN =2W • same pull-up and pull-down currents • approx. equal resistances RN = RP • approx. equal rise tpLH and fall tpHL delays • Analyze as an RC network 2W W tpHL = (ln 2) RNCL Delay (D): tpLH = (ln 2) RPCL Load for the next stage:

  22. Inverter with Load Delay RW CL RW Load (CL) tp = kRWCL k is a constant, equal to 0.69 Assumptions: no load -> zero delay Wunit = 1

  23. Inverter with Load CP = 2Cunit Delay 2W W Cint CL Load CN = Cunit Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint) = Delay (Internal) + Delay (Load)

  24. Delay Formula Cint = gCgin withg 1 f = CL/Cgin- effective fanout R = Runit/W ; Cint =WCunit tp0 = 0.69RunitCunit

  25. Apply to Inverter Chain In Out CL 1 2 N tp = tp1 + tp2 + …+ tpN

  26. Optimal Tapering for Given N • Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N • Minimize the delay, find N - 1 partial derivatives • Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1 • Size of each stage is the geometric mean of two neighbors • each stage has the same effective fanout (Cout/Cin) • each stage has the same delay

  27. Optimum Delay and Number of Stages When each stage is sized by f and has same eff. fanout f: Effective fanout of each stage: Minimum path delay

  28. Example In Out CL= 8 C1 1 f f2 C1 CL/C1 has to be evenly distributed across N = 3 stages:

  29. Optimum Number of Stages For a given load, CL and given input capacitance Cin Find optimal sizing f For g = 0, f = e, N = lnF

  30. Optimum Effective Fanout f Optimum f for given process defined by g fopt = 3.6 forg=1

  31. Buffer Design N f tp 1 64 65 2 8 18 3 4 15 4 2.8 15.3 1 64 1 8 64 1 4 64 16 1 64 22.6 8 2.8

  32. Power Dissipation

  33. Where Does Power Go in CMOS?

  34. Vdd Vin Vout C L Dynamic Power Dissipation 2 Energy/transition = C * V L dd 2 Power = Energy/transition * f = C * V * f L dd Not a function of transistor sizes! Need to reduce C , V , and f to reduce power. L dd

  35. Node Transition Activity and Power

  36. Short Circuit Currents

  37. How to keep Short-Circuit Currents Low? Short circuit current goes to zero if tfall >> trise, but can’t do this for cascade logic, so ...

  38. Minimizing Short-Circuit Power Vdd =3.3 Vdd =2.5 Vdd =1.5

  39. Static Power Consumption Wasted energy … Should be avoided in almost all cases, but could help reducing energy in others (e.g. sense amps)

  40. Leakage Currents Sub-threshold current one of most compelling issues in low-energy circuit design!

  41. Reverse-Biased Diode Leakage JS = 10-100 pA/mm2 at 25 deg C for 0.25mm CMOS JS doubles for every 9 deg C!

  42. Total Power Consumption Ptot = Pdyn + Pdp + Pstat = (CLVDD + VDD Ipeak ts)f0-1 + VDD Ileak Ipeak = Maximum short circuit current Ts = 0-100% transition time of Ipeak Ileak = The current that flows between the supply rails in the absence of switching activity. 2

  43. Principles for Power Reduction • Prime choice: Reduce voltage! • Recent years have seen an acceleration in supply voltage reduction • Design at very low voltages still open question (0.6 … 0.9 V by 2010!) • Reduce switching activity • Reduce physical capacitance • Device Sizing: for F=20 • fopt(energy)=3.53, fopt(performance)=4.47

  44. Impact ofTechnology Scaling

  45. Goals of Technology Scaling • Make things cheaper: • Want to sell more functions (transistors) per chip for the same money • Build same products cheaper, sell the same part for less money • Price of a transistor has to be reduced • But also want to be faster, smaller, lower power

  46. Technology Scaling • Goals of scaling the dimensions by 30%: • Reduce gate delay by 30% (increase operating frequency by 43%) • Double transistor density • Reduce energy per transition by 65% (50% power savings @ 43% increase in frequency • Die size used to increase by 14% per generation • Technology generation spans 2-3 years

  47. Year of Introduction 1999 2000 2001 2004 2008 2011 2014 Technology node [nm] 180 130 90 60 40 30 Supply [V] 1.5-1.8 1.5-1.8 1.2-1.5 0.9-1.2 0.6-0.9 0.5-0.6 0.3-0.6 Wiring levels 6-7 6-7 7 8 9 9-10 10 Max frequency [GHz],Local-Global 1.2 1.6-1.4 2.1-1.6 3.5-2 7.1-2.5 11-3 14.9 -3.6 Max mP power [W] 90 106 130 160 171 177 186 Bat. power [W] 1.4 1.7 2.0 2.4 2.1 2.3 2.5 Technology Evolution (2000 data) International Technology Roadmap for Semiconductors Node years: 2007/65nm, 2010/45nm, 2013/33nm, 2016/23nm

  48. ITRS Technology Roadmap

  49. Terminology • ITRS: International Technology Roadmap for Semiconductors. It is devised and intended for technology assessment only and is without regard to any commercial considerations pertaining to individual products or equipment • DRAM Half-pitch: The common measure of the technology generation of a chip. It is half the distance between cells in a dynamic RAM memory chip. For example, in 2002, the DRAM half pitch has been reduced to 130 nm (.13 micron).

  50. Half Pitch

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