خانواده هاي FPLD

1. خانواده هاي FPLD مرتضي صاحب الزماني

2. Cyclone FPGA • SRAM-based مرتضي صاحب الزماني

3. Altera Cyclone Devices مرتضي صاحب الزماني

4. Cyclone V Architecture Gigabit Transceiver Blocks مرتضي صاحب الزماني

5. Cyclone V Architecture مرتضي صاحب الزماني

6. LAB Structure • LAB: • 10 ALMs • Logic implementation • Local interconnect: • Fast connection between ALMs • MLAB (Memory LAB): • Can be configured as 32x2 dual port SRAM. مرتضي صاحب الزماني

7. ALM Structure مرتضي صاحب الزماني

8. Cyclone V مرتضي صاحب الزماني

9. Cyclone V Characteristics مرتضي صاحب الزماني

10. On-Chip Memory • MLAB Blocks: • Wide and shallow • 640-bit blocks • 10 ALMs: • Each 32 x 2 bit blocks • Configured as shift registers and FIFO. • M10K Blocks: • 10 Kb blocks مرتضي صاحب الزماني

11. Memory Resources • One type of chips مرتضي صاحب الزماني

12. Memory Resources • Configurations in single/dual-port modes مرتضي صاحب الزماني

13. M10K Port Modes • Single-Port: • Only one read or one write operation at a time • Simple Dual-Port: • Can simultaneously perform one read and one write operations to different locations • True Dual-Port: • Can perform any combination of two port operations: • Two reads, two writes, or one read and one write at two different clock frequencies. مرتضي صاحب الزماني

14. Computational Blocks • DSP Blocks: • Multiplication • 27 x 27 • 18 x 18 • 9 x 9 • Add/subtract, accumulation • Efficient calculation of Σ xi . yi • Constant storage: • No need to input from external ports in run-time مرتضي صاحب الزماني

15. DSP Block مرتضي صاحب الزماني

16. FIR (Finite Impulse Response) Filter y[n] = C0.x[n] + C1.x[n-1] + … + CN.x[n-N]

17. Cyclone V مرتضي صاحب الزماني

18. Inferring Multipliers • In Quartus II: • Use attribute syn_multstyle: • lpm_mult: • Multipliers implemented in DSP blocks • logic: • Multipliers implemented as LEs مرتضي صاحب الزماني

19. Inferring Multipliers architecture beh of onereg is signal temp : std_logic_vector (15 downto 0); attribute syn_multstyle : string; attribute syn_multstyle of temp : signal is "logic"; begin temp <= a * b; r <= temp when en='1' else c; end beh; مرتضي صاحب الزماني

20. Inferring Multipliers • In XST: • Use attribute mult_style: • auto: (default) • XST looks for the best implementation • block: • Multipliers implemented as DSP block • lut: • Multipliers implemented as LUTs مرتضي صاحب الزماني

21. Inferring Multipliers architecture beh of onereg is signal temp : std_logic_vector (15 downto 0); attribute mult_style: string; attribute mult_style of temp : {signal|entity } is "{auto|block|lut|pipe_lut}"; begin temp <= a * b; … end beh; مرتضي صاحب الزماني

22. Hard Processor Core • Some chips: Arm Cortex-9 • Single- or dual-core processor with up to 925 MHz maximum frequency • Hardened embedded peripherals • Hardened protocol PCIe • Hardened multiport memory controller, shared by the processor and FPGA logic, supports DDR2, DDR3, and LPDDR2 devices • Level-1 cache: 32 KB • Level-2 cache: 512 KB مرتضي صاحب الزماني

23. IO Element مرتضي صاحب الزماني

24. مرتضي صاحب الزماني

25. IO Element - OCT • OCT (on-chip termination): • For impedance matching • Resistor value can be programmed • No need for on-board termination •  Large space saving مرتضي صاحب الزماني

26. IO Element – Open-Drain Outpout • Open-drain output: • Can produce hi-Z output • Needs a pull-up resistor to generate logic ‘1’ • Programmable pull-up resistor avoids on-board pull-up • Open-drain outputs can be used for wired AND مرتضي صاحب الزماني

27. IO-Element – Slew Rate • Slew rate: • Maximum rate of change of output voltage per unit of time (V/sec) • Max (dvout(t)/dt) مرتضي صاحب الزماني

28. IO-Element – Slew Rate • Slew rate: • Designer can choose fast or slow rate • Fast: for systems with high performance systems • Slow: for reliability in systems faced with high noise • At the cost of speed مرتضي صاحب الزماني

29. Clock Management • Fractional PLLs: • To avoid multiple oscillators • Programmable frequencies • Jitter/skew removal مرتضي صاحب الزماني

30. Transceiver Blocks • 3 to 12 blocks • 3.125 to 6.144 Gbps مرتضي صاحب الزماني

31. Embedded Processor • In some chips, hard processor core: • Arm Cortex-A9 • Single core, dual core • Up to 1.5 GHz • 3750 MIPS مرتضي صاحب الزماني

32. Configuration • When powered up: • Reads configuration bitstream from • An Altera-compatible EPROM • A standard EPROM • A RAM in a computer system • An intelligent processor or controller • Configuration time: • 10 to 50 ms مرتضي صاحب الزماني

33. Altera Stratix مرتضي صاحب الزماني

34. Stratix Chips • LUT-based FPGA • Logic block structure, interconnection architecture, memory blocks IO blocks, Transceiver blocks: • Very similar to Cyclone مرتضي صاحب الزماني

35. Altera FPGAs مرتضي صاحب الزماني

36. Stratix vs. Cyclone مرتضي صاحب الزماني

37. Stratix V مرتضي صاحب الزماني