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Algorithms for VLSI Design Automation. Instructor D. Zhou zhoud@utdallas.edu Phone: 972 883 4392 Office: ECN 4.610. Outline . History and the road map Traditional design flow Physical design fundamentals Performance issues System on chip. History and the road map. The history of IC

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algorithms for vlsi design automation

Algorithms for VLSI Design Automation

Instructor D. Zhou zhoud@utdallas.eduPhone: 972 883 4392Office: ECN 4.610

outline
Outline
  • History and the road map
  • Traditional design flow
  • Physical design fundamentals
  • Performance issues
  • System on chip

Dragon Star Shot Course

history and the road map
History and the road map
  • The history of IC
    • The invention of transistor
    • The invention of integrated circuit
    • IC has changed our life
  • Moore’s Law
    • IC performance and complexity have been doubled in every two years
  • Road Map

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the invention of transistor
The invention of transistor
  • John Bardeen, Walter Brattain & Wiliam Shockley in vented “The first transistor” in 1947.

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the invention of integrated circuit
The invention of integrated circuit
  • Jack Kilby & Robert Noyce inveted “The Integrated Circuit” in 1958.

Dragon Star Shot Course

moore s law
Moore’s Law
  • In 1965, Gordon Moore predicted that the number of transistors that can be integrated on a die would double every 18 to 14 months (i.e., grow exponentially with time).
  • Amazingly visionary – million transistor/chip barrier was crossed in the 1980’s.
    • 2300 transistors, 1 MHz clock (Intel 4004) - 1971
    • 16 Million transistors (Ultra Sparc III)
    • 42 Million, 2 GHz clock (Intel P4) - 2001
    • 140 Million transistor (HP PA-8500)
moore s law in microprocessors

1000

2X growth in 1.96 years!

100

10

P6

Pentium® proc

486

1

Transistors (MT)

386

0.1

286

8086

8085

0.01

8080

8008

4004

0.001

1970

1980

1990

2000

2010

Year

Moore’s Law in Microprocessors

Transistors on lead microprocessors double every 2 years

Courtesy, Intel

evolution in dram chip capacity

human memory

human DNA

book

encyclopedia

2 hrs CD audio

30 sec HDTV

page

Evolution in DRAM Chip Capacity

4X growth every 3 years!

0.07 m

0.1 m

0.13 m

0.18-0.25 m

0.35-0.4 m

0.5-0.6 m

0.7-0.8 m

1.0-1.2 m

1.6-2.4 m

die size growth

100

P6

Pentium ® proc

486

10

Die size (mm)

386

286

8080

8086

~7% growth per year

8085

8008

~2X growth in 10 years

4004

1

1970

1980

1990

2000

2010

Year

Die Size Growth

Die size grows by 14% to satisfy Moore’s Law

Courtesy, Intel

clock frequency
Clock Frequency

Lead microprocessors frequency doubles every 2 years

10000

2X every 2 years

1000

P6

100

Pentium ® proc

486

Frequency (Mhz)

386

10

8085

286

8086

8080

1

8008

4004

0.1

1970

1980

1990

2000

2010

Year

Courtesy, Intel

power dissipation
Power Dissipation

Lead Microprocessors power continues to increase

100

P6

Pentium ® proc

10

486

286

8086

Power (Watts)

386

8085

1

8080

8008

4004

0.1

1971

1974

1978

1985

1992

2000

Year

Power delivery and dissipation will be prohibitive

Courtesy, Intel

power density

10000

1000

Rocket

Nozzle

100

Nuclear

Power Density (W/cm2)

Reactor

8086

10

4004

P6

Hot Plate

8008

Pentium® proc

8085

386

286

486

8080

1

1970

1980

1990

2000

2010

Year

Power Density

Power density too high to keep junctions at low temp

Courtesy, Intel

technology trend
Technology Trend

International Technology Roadmap

for Semiconductors (ITRS)

traditional design flow
Traditional design flow
  • Traditional design flow (see slides design-flow)
  • What has not been addressed in depth
    • Understand application
    • Architecture synthesis
    • Verification is not complete

Dragon Star Shot Course

performance issues
Performance issues
  • Speed
  • Noise
  • Clock distribution
  • Power distribution
  • Low power

Dragon Star Shot Course

slide20
SOC
  • A low cost solution
  • Challenges
    • Modeling
    • Simulation
    • Mixed signal
    • Different processing
    • Timing

Dragon Star Shot Course

agenda
Agenda
  • Dealing with technology
    • Masks
    • Front-end manufacturing
    • Back-end manufacturing
  • Application requirements
  • Putting it all together

Dragon Star Shot Course

agenda1
Agenda
  • Dealing with technology
    • Masks
    • Front-end manufacturing
    • Back-end manufacturing
  • Application requirements
  • Putting it all together

Dragon Star Shot Course

semiconductor process flow

Mask Data

Design

Semiconductor Process Flow

Masks $2.8B

EDA $3.6B

Systems $1050B

  • Manufacturing $2.3B
  • Tools $0.5B
  • Computers
  • Communications
  • Consumer
  • Industrial, Military…

EDA $2.7BComp Platforms

Masks

Front-End Manufacturing $24B

Embedded SW $0.8B

  • Process Auto $1B
  • Lithography $6B
  • Etch/Doping $6B
  • Diffusion $1B
  • Deposition $5B
  • Other (CMP, Ion, Photoresist, etc.) $5B

IP $0.9B

Semiconductors $119B

  • Micros, DSP $45B
  • Memory $25B
  • ASIC, ASSP $25B
  • Analog, Discrete $25B

Wafer $4B

Back-End Manufacturing $6B

  • Bonding $1B
  • Packaging $2B
  • Test equipment $3B

Chips

Dragon Star Shot Course

Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates

exploding mask costs

Data

16GB

64GB

256GB

1024GB

Exploding Mask Costs

Year

1999

2002

2004

2007

  • Raster scan patterning exposure time for a 110mm x 110 mm mask is 6.5 hrs and 20 hrs with fine granularities (60nm vs. 120nm pixel size)
  • Largest cost contribution to mask making is mask exposure time (capital cost ~$20M)
  • RET is being absorbed by CAD vendors into layout verification / tape-out suites.
  • RET may move up into routing, placement

Node

.18µm

.13µm

.9µm

.065µm

Cost

$200-400K

$500K-1M

$800K-1.2M

$1-2M

Dragon Star Shot Course

Source: Thomas Weisel Partners

front end processing
Front-End Processing

Masks $2.8B

EDA $3.6B

Systems $1050B

Mask Data

  • Manufacturing $2.3B
  • Tools $0.5B

Design

  • Computers
  • Communications
  • Consumer
  • Industrial, Military…

EDA $2.7BComp Platforms

Masks

Front-End Manufacturing $24B

Embedded SW $0.8B

  • Process Auto $1B
  • Lithography $6B
  • Etch/Doping $6B
  • Diffusion $1B
  • Deposition $5B
  • Other (CMP, Ion, Photoresist, etc.) $5B

IP $0.9B

Semiconductors $119B

  • Micros, DSP $45B
  • Memory $25B
  • ASIC, ASSP $25B
  • Analog, Discrete $25B

Wafer $4B

Back-End Manufacturing $6B

  • Bonding $1B
  • Packaging $2B
  • Test equipment $3B

Chips

Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates

Dragon Star Shot Course

interconnect
Interconnect
  • Exploding number of metal layers, mask cost
  • Large number of vias diminishes yield
  • Increasingly complex process rules
    • Via
      • Stack
      • Multiple
      • Array
    • Metal
      • Min, max, spacing, width
    • Antenna
    • Signal EM
      • Number of vias for a given load, frequency
  • Include pattern density & shape management in layout, extraction
  • Limit vias / multiple vias

Dragon Star Shot Course

cd variation across a wafer wafer map for no dpc horizontal isolated structures

x 10-7

2.3

2.2

LineWidth [nm]

2.1

2.0

1.9

1.8

150

60

100

40

50

20

Wafer Y

0

0

Wafer Y

CD Variation Across a Wafer Wafer Map for No-DPC Horizontal Isolated Structures

Incorporate analysis of timing variation into extraction & static timing analysis

Dragon Star Shot Course

Source: Spanos, UCB

physical design for yield reliability

Insert redundant vias

  • Space / Width
Physical design for Yield / Reliability
  • Aggressive via minimization in routing
  • Limit Current Density

Dragon Star Shot Course

back end assembly and packaging
Back-End: Assembly and Packaging

Masks $2.8B

EDA $3.6B

Systems $1050B

Mask Data

  • Manufacturing $2.3B
  • Tools $0.5B

Design

  • Computers
  • Communications
  • Consumer
  • Industrial, Military…

EDA $2.7BComp Platforms

Masks

Front-End Manufacturing $24B

Embedded SW $0.8B

  • Process Auto $1B
  • Lithography $6B
  • Etch/Doping $6B
  • Diffusion $1B
  • Deposition $5B
  • Other (CMP, Ion, Photoresist, etc.) $5B

IP $0.9B

Semiconductors $119B

  • Micros, DSP $45B
  • Memory $25B
  • ASIC, ASSP $25B
  • Analog, Discrete $25B

Wafer $4B

Back-End Manufacturing $6B

  • Bonding $1B
  • Packaging $2B
  • Test equipment $3B

Chips

Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates

Dragon Star Shot Course

assembly and packaging
Assembly and Packaging
  • The chip is assembled into a package that provides the contact leads for the chip. A wire-bonding machine attaches wires to the leads of the package; or this is achieved using flip chip die attach.
  • Modern packages can be very complex
  • The package is the bridge between silicon and system
  • Differentiator: Performance, form factor, fit, thermal conduction, reliability, and cost

Dragon Star Shot Course

ic package co design for flip chip
IC / Package Co-Design for Flip Chip

Lid

Chip

Package

Pwr, Gnd

Signal

Solder

balls

Board

  • Design
    • Package feasibility
    • Bump patterning, assignment
    • P/G assignment
    • Driver placement
    • Routing
  • Analyis
    • Extraction RLC
    • Simulation Spice

Dragon Star Shot Course

soc packaging
SoC Packaging
  • Trends by 2005
    • Cost: 0.29¢ to 2.28¢ / pin
    • Pins / package: 120 – 3000
    • Performance: 600 MHz – 2GHz
  • Integrating complete (sub)systems on a chip is often driven by packaging
    • Less I/O, power, area, & cost
    • Higher on-chip speed, reliability
  • Complex packages and Multi-chip modules that require routing and analysis, driven by mixed-signal, RF, memory integration

Dragon Star Shot Course

back end testing and automatic test equipment
Back-End: Testing and Automatic Test Equipment

Masks $2.8B

EDA $3.6B

Systems $1050B

Mask Data

  • Manufacturing $2.3B
  • Tools $0.5B

Design

  • Computers
  • Communications
  • Consumer
  • Industrial, Military…

EDA $2.7BComp Platforms

Masks

Front-End Manufacturing $24B

Embedded SW $0.8B

  • Process Auto $1B
  • Lithography $6B
  • Etch/Doping $6B
  • Diffusion $1B
  • Deposition $5B
  • Other (CMP, Ion, Photoresist, etc.) $5B

IP $0.9B

Semiconductors $119B

  • Micros, DSP $45B
  • Memory $25B
  • ASIC, ASSP $25B
  • Analog, Discrete $25B

Wafer $4B

Back-End Manufacturing $6B

  • Bonding $1B
  • Packaging $2B
  • Test equipment $3B

Chips

Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates

Dragon Star Shot Course

key trends
Key Trends
  • By 2005
    • Cost: $2-5k/pin ( high performance)
    • Pins / package: 1900
    • Performance: up to 2 GHZ
  • Tester timing accuracy growing at 12% per year
  • ASIC speeds growing at 30% per year
  • IDDQ becoming less meaningful
    • For every 80mV of VT decrease Ioff increases 10x!!
    • Higher leakage currents make IDDQ values increase dramatically as transistor density increases
  • More mixed-signal testing

Dragon Star Shot Course

agenda2
Agenda
  • Dealing with technology
    • Masks
    • Front-end manufacturing
    • Back-end manufacturing
  • Application requirements
  • Putting it all together

Dragon Star Shot Course

application requirements
Application Requirements

Masks $2.8B

EDA $3.6B

Systems $1050B

Mask Data

  • Manufacturing $2.3B
  • Tools $0.5B

Design

  • Computers
  • Communications
  • Consumer
  • Industrial, Military…

EDA $2.7BComp Platforms

Masks

Front-End Manufacturing $24B

Embedded SW $0.8B

  • Process Auto $1B
  • Lithography $6B
  • Etch/Doping $6B
  • Diffusion $1B
  • Deposition $5B
  • Other (CMP, Ion, Photoresist, etc.) $5B

IP $0.9B

Semiconductors $119B

  • Micros, DSP $45B
  • Memory $25B
  • ASIC, ASSP $25B
  • Analog, Discrete $25B

Wafer $4B

Back-End Manufacturing $6B

  • Bonding $1B
  • Packaging $2B
  • Test equipment $3B

Chips

Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates

Dragon Star Shot Course

heterogeneity soc
Analog

RF

Power

MEMs

IP

Digital

Control

µP

DSP

Interfaces

Memory

SRAM

DRAM

FLASH

Heterogeneity - SoC

Dragon Star Shot Course

what eda must provide
What EDA Must Provide…
  • System level design
  • Soc design&test, verification methodology
  • Need hierarchy in the design flow
  • Analog, digital, RF, MEMs
  • IP for soc construction / verification: processors, memory, peripherals, etc.
  • Soc design for debug (debug busses and controllers)

Dragon Star Shot Course

asic assp asip ga fpga
ASIC, ASSP, ASIP, GA, FPGA
  • ASIC & ASSP differ only by how they are sold and used, not by how they are designed
  • Early market characteristics  ASICs
  • Late market characteristics  ASSPs
  • Trend toward application-specific instruction processors
    • Many processors on a chip
  • Metal Programmability (GA) gaining attention again
  • SW Programmable (FPGA), reconfigurable parts gaining importance
  • Embedded FPGA / GA

Dragon Star Shot Course

power
Power

1400

Dynamicpower

density

1200

1000

800

mW/mm2

600

Leakage power

density

400

200

0

0.18 µm

0.13 µm

0.10 µm

0.05 µm

Dragon Star Shot Course

solutions for low power design
Solutions for Low Power Design
  • Power modeling and analysis
  • Clock gating and clock tree optimization
  • Variable Vdd
    • Power gating
    • Multi - Vdd
    • Dynamic voltage scaling
  • Leakage optimization using multi-Vt
  • Modelling process variation
  • Support Asynchronous design

Dragon Star Shot Course

dual vt
Dual Vt

130nm

180nm

Leakage power [0.0-240.0] nW

Leakage power [0.0-1.0] nW

Cell number [0-519]

Cell number [0-467]

typical version

Dragon Star Shot Course

From Ali Dasdan

speed

V

D

V =

IR

R

dd

V

-

D

V

I

dd

R

V

ss

Speed
  • Determined by interconnect
  • The primary physical effect of concern is cross-coupled capacitance plus the Miller effect. This may cause:
    • functional errors in analog circuitry or dynamic logic
    • timing errors in static digital circuitry
  • IR Drop (static leakage and dynamic IR drop) handled in power
  • Other important effects & features are Inductance, CD variation, EM

Dragon Star Shot Course

agenda3
Agenda
  • Dealing with technology
    • Masks
    • Front-end manufacturing
    • Back-end manufacturing
  • Application requirements
  • Putting it all together

Dragon Star Shot Course

putting it all together eda
Putting it All Together: EDA

Masks $2.8B

EDA $3.6B

Systems $1050B

Mask Data

  • Manufacturing $2.3B
  • Tools $0.5B

Design

  • Computers
  • Communications
  • Consumer
  • Industrial, Military…

EDA $2.7BComp Platforms

Masks

Front-End Manufacturing $24B

Embedded SW $0.8B

  • Process Auto $1B
  • Lithography $6B
  • Etch/Doping $6B
  • Diffusion $1B
  • Deposition $5B
  • Other (CMP, Ion, Photoresist, etc.) $5B

IP $0.9B

Semiconductors $119B

  • Micros, DSP $45B
  • Memory $25B
  • ASIC, ASSP $25B
  • Analog, Discrete $25B

Wafer $4B

Back-End Manufacturing $6B

  • Bonding $1B
  • Packaging $2B
  • Test equipment $3B

Chips

Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates

Dragon Star Shot Course

soc design

Synthesis

Physical

Power

Test

IP

SoC Design

Design Services

Architecture Design

Design Planning

Verification IP

Languages

Assertions and Testbenches

Design Database

Timing and Signal Integrity

Physical Implementation

Smart Verification

Extraction

Physical Verification

Mixed Signal / Analog

Mask Synthesis / OPC

Dragon Star Shot Course

implementation nodes
Implementation Nodes

Dragon Star Shot Course

implementation nodes1
Implementation Nodes

Dragon Star Shot Course

functional verification

ArchitectureDesign

Languages

Assertions and Testbenches

SmartVerification

Verification IP

Mixed Signal /Analog

Functional Verification
  • Driven by complexity
  • Verification models (IP)
  • Avenues of development
    • Higher levels
    • Performance
    • Integration
    • New (formal) technologies
  • Emulation competes with
    • Prototyping (enabled by multi-million gate FPGAs)
    • Compute farms (Linux)

Dragon Star Shot Course

functional verification 2003

ArchitectureDesign

Languages

Assertions and Testbenches

SmartVerification

Verification IP

Mixed Signal /Analog

Functional Verification 2003
  • Standard based IP, Star IP on AMBA
  • (System) Verilog for HW
  • SystemC for system level design (SW)
  • Languages for testbenches, assertions being standardized
  • Integrated simulation
    • (System)Verilog/VHDL
    • Fast Spice/Spice
  • Testbenches
    • Language
    • Assertions (monitor)
    • Constraint solver
  • Formal verification
    • Equivalence checking
    • Semi-Formal property checking

Dragon Star Shot Course

summary
Summary
  • Dealing with technology
    • Masks
      • RET, OPC, PSM
    • Front-end manufacturing
      • Interconnect, CD variation, dishing, DFM
    • Back-end manufacturing
      • Packaging, test
  • Application requirements
    • Heterogeneity, cost, power, speed
  • Putting it all together
    • Implementation flow, verification flow

Dragon Star Shot Course