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Explore the world of Verilog, VHDL, and Bluespec while learning about FPGA execution, HDL design processes, and formal verification tools. Understand the challenges people face with HDL syntax and embrace the power of abstraction for simpler, more expressive digital logic designs. Dive into HDL optimization, synthesis, and FPGA implementation for efficient hardware development. Uncover the role of PLI in bridging hardware and software languages for seamless integration. Discover team dynamics and tools for effective collaboration in computer architecture labs.
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Verilight Adam S. Waksman Richard A. Sampson Chisom N. Maduike Malcolm T. Bressendorf Albert L. Jimenez
Background on HDLs Formal description of digital logic Verilog, VHDL, Bluespec Complete Parallelism Convert directly to hardware Execute on FPGA Fabricate physical chip Fujitsu
Computer Architecture Lab HDLs: Design Process Block Diagram Coding FPGA Netlist Source Code Compilation Synthesis
Why People Hate HDLs “I have checked out a ton of different HDLs and why does every single one of them require a lot of code to do 1 thing, and why is their syntax so radically different from everything that exists for regular programming?” -XKCD Forums User
Why People Hate HDLs “I have checked out a ton of different HDLs and why does every single one of them require a lot of code to do 1 thing, and why is their syntax so radically different from everything that exists for regular programming?” -XKCD Forums User
Salvation through Abstraction Analogy: OpenGL Abstracted away pixels and points Libraries and Objects Simple code for what users want Verilight Abstracted away wires and registers Simple code for synchronous digital logic design Microprocessors Peripherals IP Units
Abstraction and Expressiveness define combo pc_template: pc = pc + 4; pc_out = pc; specify pc = pc_template(pc=32); module pc_module(clk, nrst, pc_out); input clk; input nrst; output [31:0] pc_out; reg [31:0] pc; wire [31:0] pc_val; wire [31:0] sum; assign sum = pc_val + 32'b100; assign pc_val = pc; assign pc_out = pc_val; always @(posedge clk) begin if(nrst == 1'b0) begin pc <= 32'b0; end if(nrst == 1'b1) begin pc <= sum; end end endmodule
Features specify two_adders = adder(2); define arch MyCoolArch: in → two_adders; two_adders → ff → divider; divider → ff → out; count divider in DivCount; count two_adders in AddCount; assert DivCount == AddCount; • Object Orientation • Combo/Arch • Templates/Polymorphism • Block Diagrams • Syntax forces block structure • Scope maintained throughout a block • Code Analysis • Semantically meaningful blocks • Automated Stat Tracking • Motivation: Intel PTU • Automated Testing • Stimulus/GTK Wave • Dynamic Hardware Assertions • For debugging and verification • Motivation: HOST
Computer Architecture Lab Verification • Informal Verification • Waveform viewer • Simulation on Quartus • Textual Analysis using scripts • Formal Verification • Programming Language Interface (PLI) • Interface between generated Verilog code and a model written in C
Computer Architecture Lab Verification: PLI
Lessons Learned Languages A lot more to it than we thought Many layers HDLs Can be made simpler, more abstract Team Delegation Teamwork important Hard to orchestrate clashing schedules
