Status of the MicroTCA TDC developments at FZ Jülich

1. Status of the MicroTCA TDC developments at FZ Jülich H. Kleines, M. Drochner, A. Ackens, P. Wüstner, P. Kämmerling, W.Erven Zentralinstitut für Elektronik (ZEL), Forschungszentrum Jülich

2. Background • Pragmatic approach for PANDA DAQ: Start with MicroTCA • First Development: TDC module with GPX ASIC from acam messelektronik gmbh, because of existing experience from WASA electronics • Possible use for STT • Major delay in development because of access to standards • FZ Jülich became PICMG member in the middle of December 2008, finally

3. Design changes • Original plans: • 16 channels • Single width, compact size module • Smallest Virtex5FXT: XC5VLX20T • Acquire MMC from PidgeonPoint • Now: • 32 channels: because of price/channel • Double width, compact size module • XC5VLX30T with FF665 package (150 €, now 280€!!) • Implement MMC ourselves using a microcontroller

4. Design Decisions • Implement AMC.1 • Connect AMC ports 4 to 7 to Virtex5 GTP_Dual Tiles X0Y3 und X0Y2 and implement 4 PCIe lanes using the embedded PCIe endpoint. Use FCLKA as reference clock. • For backward compatibility connect AMC port 0 to GTP_Dual Tile X0Y0. Using the embedded MAC core GbE could be implemented • No private rear IO (DAC control only via front conn.) • Clock and Start signals from front connector or FPGA • Still discussing use of Telecom clocks • Use card edge connector

5. GPX2 GPX4 GPX3 GPX1 PIC32 XC5VLX30T ECL/LVPECL/LVDS to LVTTL 32 STOP Block diagram Start + clock DAC,… • MMC will implemented by Microchip PIC32MX460F512L Microcontroller with 2 integrated I2C interfaces • major issue!!! PCIe (4 Lanes) T.CLOCK A,B GbE (Option) div. Signals I2C

6. Status I • Layout finished and PCB available • HW testing started with Microcontroller part

7. Status II • Test system has been ordered from Powerbridge and ELMA (ca. 20.000 €) • Crates from Schroff and Elma • CPUs from ADLINK and Emerson • MCHs from NAT and Emerson • PMC and IP carrier modules • Most components arrived during the last two weeks • Major work items • FPGA code (not yet started) • MMC code (not yet started)

8. Overview of the GPX ASIC • 2 Packages: • Core: PLL-stabilized ring-oscillator • Several modes: bin-size 10 ps to 81 ps • I-Mode: • Bin-size: typ. 81 ps • Dynamic range: 17 Bit • 32fold multihit-capable, double-pulse resolution ca. 5,5 ns • Peak-Rate: 182 MHit/s • Continuous rate per channel: 10 MHit/s • Continuous rate over all channels: 40 MHit/s • Inputs: LVTTL • No trigger-matching-unit

9. GPX Structure • Transfer to hit HIFO: 182 MHz • Transfer to Interface FIFO: 10 MHz • Data bus: 40 MHz • Internally retriggerable

10. 64 LVDS/diff. ECL inputs GPX8 GPX7 GPX6 GPX5 GPX4 GPX3 GPX2 GPX1 FPGA (Spartan 3) Diff. ECL to TTL Existing WASA TDC Electronics with GPX ASIC • GPX (successor of F1 from acam messelectronic GmbH in I-Mode): 8 channels, 81ps bin-size, 10 MHit/s per channel • Crate-wide synchronization via ECL-Signals on the backplane • Control signals for frontend-eletronic via rear transition modules • Inputs LVTTL => Mezzanines for LVDS and diff. ECL • Trigger matching in FPGA LVD-Bus ECL Sync to TM