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Lab III. Real-Time Embedded Operating System for a SoC System. Startup Flow Chat. initialization Stack LDR r7, #RAMBased MRS r4, cpsr ORR r4, r4, #NoIRQ ORR r4, r4, #NoFIQ BIC r4, r4, #ModeMask Clear Mode MOV r2, #User32Mode

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lab iii

Lab III

Real-Time Embedded

Operating System for a SoC

System

startup flow chat
Startup Flow Chat

initialization Stack

LDR r7, #RAMBased

MRS r4, cpsr

ORR r4, r4, #NoIRQ

ORR r4, r4, #NoFIQ

BIC r4, r4, #ModeMask Clear Mode

MOV r2, #User32Mode

;--------------------------------------------------

ORR r5, r4, #IRQ32Mode

MSR cpsr_c, r5

MSR spsr_c, r2

MOV sp, r7 ; Initial IRQ stack pointer...

SUB r7, r7, #IRQStackSize

....;;Set SVC Mode Stack pointer

;;Set User Mode Stack pointer

Reset

Building

Exception Handler

Set INTMSK ;Disable IRQClear INTPND

Initiation Stack Pointer

for Exception mode and SPSR

Execution C_function

arm exception
ARM Exception
  • ARM Exception Events
install an exception handler method
Install an Exception Handler: Method

Vector_Init_Block

b Reset_Addr

b Undefined_Addr

b SWI_Addr

b Prefetch_Addr

b Abort_Addr

NOP ;Reserved vector

b IRQ_Addr

b FIQ_Addr

Reset_Addr …

Undefined_Addr …

B .For loop

SWI_Addr …

Prefetch_Addr …

B . For loop

Abort_Addr …

IRQ_Addr …

FIQ_Addr …

install an exception handler method1
Install an Exception Handler: Method

Vector_Init_Block

LDR PC, Reset_Addr

LDR PC, Undefined_Addr

LDR PC, SWI_Addr

LDR PC, Prefetch_Addr

LDR PC, Abort_Addr

NOP ;Reserved vector

LDR PC, IRQ_Addr

LDR PC, FIQ_Addr

Reset_Addr DCD Start_Boot

Undefined_Addr DCD Undefined_Handler

SWI_Addr DCD SWI_Handler

Prefetch_Addr DCD Prefetch_Handler

Abort_Addr DCD Abort_Handler

DCD 0 ;Reserved vector

IRQ_Addr DCD IRQ_Handler

FIQ_Addr DCD FIQ_Handle

Start_Boot

LDR …

Undefined_Handler

B . (for loop)

swi exception and handler
SWI Exception and Handler
  • Top-Level SWI Handlers
    • The SWI number is stored in bits 0-23 of the instruction
      • Save all other r0~r12andlrto the stack
      • Calculate the SWI number
      • Jump Your Handler
      • Return
    • void__swi(n) SWI_Name(void); for C Call
swi handler flow
SWI_Handler Flow

SWI_Handler ; top-level handler

STMFD sp!,{r0-r12,lr} ; Store registers.

LDR r0,[lr,#-4] ; Calculate address of SWI instruction

; and load it into r0.

BIC r0,r0,#0xff000000 ; Mask off top 8 bits of instruction

;to give SWI number.

;

; Use value in r0 to determine which SWI routine to execute.

; BNE after

; Branch You Handler

;

; Branch your Handler

LDMFD sp!, {r0-r12,pc}^ ; Restore registers and return

irq handler flow
IRQ Handler Flow

IRQ_Handler ; top-level handler

STMFD sp!,{r0-r12,lr} ; Store registers.

BL ISR_IRQ

LDMFD sp!, {r0-r12,pc} ; Restore registers and return

SUBS pc, lr, #4

s3c4510b interrupt sources
S3C4510B Interrupt Sources
  • S3C4510B Interrupt Sources
samsung s3c4510b interrupt controller
Samsung S3C4510B InterruptController
  • Five special registers used to control the interrupt generation and handling
    • Interrupt mode register
      • Defines the interrupt mode, IRQ(0) or FIQ(1), for each interrupt source.
    • Interrupt pending register
      • Indicates that an interrupt request is pending
    • Interrupt mask register
      • The current interrupt is disabled if the corresponding mask bit is "1“
      • If the global mask bit (bit 21) is set to "1", no interrupts are serviced.
    • Interrupt priority registers
    • Interrupt offset register
      • Determine the highest priority among the pending interrupts.
interrupt mask register intmsk
Interrupt Mask Register (INTMSK)
  • If global mask bit (bit 21) is 1, no interrupts are serviced
  • If bit is 1, the interrupt is not serviced by the CPU when the corresponding interrupt is generated
interrupt pending register
Interrupt pending register
  • Each of the 21 bits corresponds to an interrupt source
    • The service routine must then clear the pending conditionby writing a 1to the appropriate pending bit at start.
    • #define Clear_PendingBit(n) INTPND_REG=(1<<n)
interrupt offset register
Interrupt offset register
  • Contains the interrupt offset addressof the interrupt
    • Hold the highest priority among the pending interrupts
    • The content of the interrupt offset address is "bit position value of the interrupt source << 2“
    • You can read this register to get the IRQNumber

#define INTOFFSET REG32(SYS_BASE+0x4024)

int currentIRQnumber=INTOFFSET >> 2;

32 bit timers
32-BIT TIMERS
  • INTERVAL MODE OPERATION
    • fTOUT = fMCLK / Timer data value
    • Example. 2 = 50 MHz /25 MHz 25MHz=2FAF080
  • TOGGLE MODE OPERATION
    • fTOUT = fMCLK / (2 * Timer data value)
timer mode register
TIMER MODE REGISTER
  • The timer mode register, TMOD, is used to control the operation of the two 32-bit timers

[0] Timer 0 enable (TE0)

0 = Disable timer 0

1 = Enable timer 0

[1] Timer 0 mode selection (TMD0)

0 = Interval mode

1 = Toggle mode

[2] Timer 0 initial TOUT0 value (TCLR0)

0 = Initial TOUT0 is 0 in toggle mode

1 = Initial TOUT0 is 1 in toggle mode

#define TMOD REG32(SYS_BASE+0x6000)

timer data registers
TIMER DATA REGISTERS
  • #define TDATA0 REG32(SYS_BASE+0x6004)
reference
Reference
  • Samsung S3C4510B User’s Manual
    • http://www.samsung.com/Products/Semiconductor/SystemLSI/Networks/PersonalNTASSP/CommunicationProcessor/S3C4510B/S3C4510B.htm
    • Chapter 7 ARM Exceptions
    • ARM 原理與實作 –以網路SOC為例