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Fundamentals of Digital System Design. Pradondet Nilagupta Lecture 8: Synchronous Sequential Circuits Chapter 8. Synchronous Sequential Circuits. Sequential circuits – outputs depend on past behavior as well as present inputs. Synchronous circuits – use a clock signal to sequence behavior.

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fundamentals of digital system design

Fundamentals of Digital System Design

Pradondet Nilagupta

Lecture 8: Synchronous Sequential Circuits

Chapter 8

synchronous sequential circuits
Synchronous Sequential Circuits
  • Sequential circuits – outputs depend on past behavior as well as present inputs.
  • Synchronous circuits – use a clock signal to sequence behavior.
  • Asynchronous circuits – no clock signal is used (see Chapter 9).
slide3
W

Combinational

Combinational

Z

Flip-flops

circuit

circuit

Q

Clock

Figure 8.1 The general form of a sequential circuit

a simple example
Clockcycle:

t

t

t

t

t

t

t

t

t

t

t

0

1

2

3

4

5

6

7

8

9

10

w

:

0

1

0

1

1

0

1

1

1

0

1

z

:

0

0

0

0

0

1

0

0

1

1

0

A Simple Example
  • Circuit has one input, w, and one output, z.
  • Changes occur on positive clock edge.
  • z is 1 if w is 1 during last two clock cycles.

Figure 8.2 Sequences of input and output signals

slide5
Reset

w

=

1

¤

¤

A

z

=

0

B

z

=

0

w

=

0

w

=

0

w

=

1

w

=

0

¤

C

z

=

1

w

=

1

Figure 8.3 State diagram of a simple sequential circuit

slide6
Next state

Present

Output

z

state

w

=

0

w

=

1

A

A

B

0

B

A

C

0

C

A

C

1

Figure 8.4 State table

slide7
Y

y

1

1

w

Combinational

Combinational

z

circuit

circuit

Y

y

2

2

Clock

Figure 8.5 A general sequential circuit

slide8
Next state

Present

Output

w

=

0

w

=

1

state

z

y

y

Y

Y

Y

Y

2

1

2

1

2

1

00

00

01

A

0

01

00

10

B

0

10

00

10

C

1

11

dd

dd

d

Figure 8.6 A State-assigned table

slide9
y

y

2

1

Ignoring don't cares

Using don't cares

00

01

11

10

w

0

0

0

d

0

Y

=

wy

y

Y

=

wy

y

1

2

1

2

1

1

1

1

0

d

0

y

y

2

1

w

00

01

11

10

0

0

0

d

0

Y

=

wy

y

+

wy

y

Y

=

wy

+

wy

2

1

2

1

2

2

1

2

1

0

1

d

1

(

)

=

w

y

+

y

1

2

y

1

y

2

0

1

0

0

0

z

=

y

y

z

=

y

1

2

2

1

1

d

Figure 8.7 Derivation of logic expressions

slide11
t

t

t

t

t

t

t

t

t

t

t

0

1

2

3

4

5

6

7

8

9

10

1

Clock

0

1

w

0

1

y

1

0

1

y

2

0

1

z

0

Figure 8.9 Timing diagram

summary of design steps
Summary of Design Steps
  • Obtain specification of the desired circuit.
  • Create a state diagram from specification.
  • Create a state table from state diagram.
  • Perform state minimization.
  • Perform state assignment.
  • Derive the next-state logic expressions.
  • Implement circuit described by logic.
slide13
Data

Extern

Bus

Clock

R

1

R

2

Rk

R

1

R

1

R

2

R

2

Rk

Rk

in

out

in

out

in

out

Control circuit

Function

Figure 7.56 A digital system with k registers

slide14
,

,

,

R

2

R

3

R

1

R

2

R

3

R

1

out

in

out

in

out

in

w

Q

Q

Q

D

D

D

Clock

Q

Q

Q

Reset

Figure 7.58 A shift-register control circuit

slide15
R

1

out

R

1

in

w

R

2

out

Control

R

2

circuit

in

R

3

out

Clock

R

3

in

Done

Figure 8.10 Signals needed in Example 8.1

slide16
w

=

0

¤

A

No

Reset

transfer

w

=

1

¤

,

B

R

2

=

1

R

3

=

1

out

in

w

=

0

w

=

1

w

=

0

w

=

1

¤

,

C

R

1

=

1

R

2

=

1

out

in

w

=

0

w

=

1

¤

,

,

D

R

3

=

1

R

1

=

1

Done

=

1

out

in

Figure 8.11 State diagram

slide17
Next state

Outputs

Present

state

w = 0

w = 1

A

A

B

0

0

0

0

0

0

0

B

C

C

0

0

1

0

0

1

0

C

D

D

1

0

0

1

0

0

0

D

A

A

0

1

0

0

1

0

1

Figure 8.12 State table

slide21
Next state

Present

Output

state

w

=

0

w

=

1

z

y

y

Y

Y

Y

Y

2

1

2

1

2

1

A

00

00

01

0

B

01

00

11

0

C

11

00

11

1

10

dd

dd

d

Figure 8.16 Improved state assignment

1

slide22
Y

y

2

2

z

Q

D

Q

Y

y

1

1

w

Q

D

Q

Clock

Resetn

Figure 8.17 Final circuit for the improved state assignment

slide24
y

y

2

1

w

00

01

11

10

0

1

Y

=

wy

+

y

y

2

2

1

1

1

1

1

y

y

2

1

w

00

01

11

10

0

1

1

Y

=

y

2

1

1

1

1

Figure 8.19 Derivation of next-state expressions

slide25
Nextstate

Present

Output

state

w

=

0

w

=

1

z

y

y

y

Y

Y

Y

Y

Y

Y

3

2

1

3

2

1

3

2

1

A

001

001

010

0

B

010

001

100

0

C

100

001

100

1

Figure 8.20 One-hot state assignment

1

slide27
Clock cycle:

t

t

t

t

t

t

t

t

t

t

t

0

1

2

3

4

5

6

7

8

9

10

w

:

0

1

0

1

1

0

1

1

1

0

1

z

:

0

0

0

0

1

0

0

1

1

0

0

Mealy State Model

  • Moore machines – output is determined only be present state.
  • Mealy machines – output depends on both present state and input values.

Figure 8.22 Sequences of input and output signals

1

slide28
Reset

¤

w

=

1

z

=

0

¤

¤

w

=

0

z

=

0

w

=

1

z

=

1

A

B

¤

w

=

0

z

=

0

z

Next state

Output

Present

state

w

=

0

w

=

1

w

=

0

w

=

1

A

A

B

0

0

B

A

B

0

1

Figure 8.23 State diagram

slide29
Next state

Output

Present

z

Next state

Output

state

Present

w

=

0

w

=

1

w

=

0

w

=

1

state

w

=

0

w

=

1

w

=

0

w

=

1

y

Y

Y

z

z

A

A

B

0

0

A

0

0

1

0

0

B

A

B

0

1

B

1

0

1

0

1

Figure 8.24 State table

slide30
z

w

Q

D

y

Clock

Q

Resetn

(a) Circuit

t

t

t

t

t

t

t

t

t

t

t

0

1

2

3

4

5

6

7

8

9

10

1

Clock

0

1

w

0

1

y

0

1

z

0

(b) Timing diagram

Figure 8.26 FSM implementation

slide32
w

=

0

Reset

A

¤

,

w

R

R

=

1

2

=

1

3

=

1

out

in

B

w

=

0

,

R

R

1

=

1

2

=

1

out

in

w

=

1

C

w

=

0

,

,

R

R

Done

3

=

1

1

=

1

=

1

out

in

w

=

1

Figure 8.28 State diagram for Example 8.4

slide33
,

,

,

R

2

R

3

R

1

R

2

R

3

R

1

out

in

out

in

out

in

Reset

w

P

Q

Q

Q

D

D

D

Q

Q

Q

Clock

Figure 7.59 A modified control circuit

design of fsms using cad tools
Design of FSMs using CAD tools
  • Could design using manual techniques then use schematic capture or structural VHDL.
  • Instead should enter state table via a state diagram editor or behavioral VHDL.
slide35
USE ieee.std_logic_1164.all ;

ENTITY simple IS

PORT ( Clock, Resetn, w : IN STD_LOGIC ;

z : OUT STD_LOGIC ) ;

END simple ;

ARCHITECTURE Behavior OF simple IS

TYPE State_type IS (A, B, C) ;

SIGNAL y : State_type ;

BEGIN

PROCESS ( Resetn, Clock )

BEGIN

IF Resetn = '0' THEN

y <= A ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

con’t ...

Figure 8.29a VHDL code for a simple FSM

slide36
CASE y IS

WHEN A =>

IF w = '0' THEN

y <= A ;

ELSE

y <= B ;

END IF ;

WHEN B =>

IF w = '0' THEN

y <= A ;

ELSE

y <= C ;

END IF ;

WHEN C =>

IF w = '0' THEN

y <= A ;

ELSE

y <= C ;

END IF ;

END CASE ;

END IF ;

END PROCESS ;

z <= '1' WHEN y = C ELSE '0' ;

END Behavior ;

Figure 8.29b VHDL code for a simple FSM (con’t)

slide37
Interconnection wires

Resetn

Clock

w

PAL-like block

1

1

0

y

1

D

Q

1

1

0

y

2

D

Q

0

1

0

z

D

Q

(Other macrocells are not shown)

Figure 8.30 Implementation of an FSM in a CPLD

slide39
(a) Timing simulation results

(b) Magnified simulation results, showing timing details

Figure 8.32 Simulation results

slide40
(ENTITY declaration not shown)

ARCHITECTURE Behavior OF simple IS

TYPE State_type IS (A, B, C) ;

SIGNAL y_present, y_next : State_type ;

BEGIN

PROCESS ( w, y_present )

BEGIN

CASE y_present IS

WHEN A =>

IF w = '0' THEN

y_next <= A ;

ELSE

y_next <= B ;

END IF ;

WHEN B =>

IF w = '0' THEN

y_next <= A ;

ELSE

y_next <= C ;

END IF ;

Figure 8.33a Alternative style of code for an FSM

slide41
WHEN C =>

IF w = '0' THEN

y_next <= A ;

ELSE

y_next <= C ;

END IF ;

END CASE ;

END PROCESS ;

PROCESS (Clock, Resetn)

BEGIN

IF Resetn = '0' THEN

y_present <= A ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

y_present <= y_next ;

END IF ;

END PROCESS ;

z <= '1' WHEN y_present = C ELSE '0' ;

END Behavior ;

Figure 8.33b Alternative style of code for an FSM (con’t)

slide42
(ENTITY declaration not shown)

ARCHITECTURE Behavior OF simple IS

TYPE State_TYPE IS (A, B, C) ;

ATTRIBUTE ENUM_ENCODING : STRING ;

ATTRIBUTE ENUM_ENCODING OF State_type : TYPE IS "00 01 11" ;

SIGNAL y_present, y_next : State_type ;

BEGIN

con’t ...

Figure 8.34 A user-defined attribute for manual state assignment

slide43
LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY simple IS

PORT ( Clock, Resetn, w : IN STD_LOGIC ;

z : OUT STD_LOGIC ) ;

END simple ;

ARCHITECTURE Behavior OF simple IS

SIGNAL y_present, y_next : STD_LOGIC_VECTOR(1 DOWNTO 0);

CONSTANT A : STD_LOGIC_VECTOR(1 DOWNTO 0) := "00" ;

CONSTANT B : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01" ;

CONSTANT C : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11" ;

BEGIN

PROCESS ( w, y_present )

BEGIN

CASE y_present IS

WHEN A =>

IF w = '0' THEN y_next <= A ;

ELSE y_next <= B ;

END IF ;

… con’t

Figure 8.35a Using constants for manual state assignment

slide44
WHEN B =>

IF w = '0' THEN y_next <= A ;

ELSE y_next <= C ;

END IF ;

WHEN C =>

IF w = '0' THEN y_next <= A ;

ELSE y_next <= C ;

END IF ;

WHEN OTHERS =>

y_next <= A ;

END CASE ;

END PROCESS ;

PROCESS ( Clock, Resetn )

BEGIN

IF Resetn = '0' THEN

y_present <= A ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

y_present <= y_next ;

END IF ;

END PROCESS ;

z <= '1' WHEN y_present = C ELSE '0' ;

END Behavior ;

Figure 8.35b Using constants for manual state assignment (cont’)

slide45
LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY mealy IS

PORT ( Clock, Resetn, w : IN STD_LOGIC ;

z : OUT STD_LOGIC ) ;

END mealy ;

ARCHITECTURE Behavior OF mealy IS

TYPE State_type IS (A, B) ;

SIGNAL y : State_type ;

BEGIN

PROCESS ( Resetn, Clock )

BEGIN

IF Resetn = '0' THEN

y <= A ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

CASE y IS

WHEN A =>

IF w = '0' THEN y <= A ;

ELSE y <= B ;

END IF ;

… con’t

Figure 8.36 VHDL code for a Mealy machine

slide46
WHEN B =>

IF w = '0' THEN y <= A ;

ELSE y <= B ;

END IF ;

END CASE ;

END IF ;

END PROCESS ;

PROCESS ( y, w )

BEGIN

CASE y IS

WHEN A =>

z <= '0' ;

WHEN B =>

z <= w ;

END CASE ;

END PROCESS ;

END Behavior ;

Figure 8.36b VHDL code for a Mealy machine (con’t)

slide49
A

a

Shift register

s

Adder

Shift register

FSM

Shift register

b

Sum

A

B

=

+

B

Clock

Figure 8.39 Block diagram of a serial adder

slide51
Next state

Output

Present

s

Next state

Output

Present

state

ab

=00

01

10

11

00

01

10

11

state

ab

=00

01

10

11

00

01

10

11

y

Y

s

G

G

G

G

H

0

1

1

0

0

0

0

0

1

0

1

1

0

H

G

H

H

H

1

0

0

1

1

0

1

1

1

1

0

0

1

Figure 8.41 State table for the serial adder

slide52
s

a

Full

b

adder

Y

y

Q

D

carry-out

Clock

Q

Reset

Figure 8.43 Circuit for the adder FSM

slide53
Reset

11

01

¤

¤

G

s

=

0

H

s

=

0

00

0

0

10

00

01

01

00

11

11

10

10

01

¤

¤

G

s

=

1

H

s

=

1

11

1

1

10

00

Figure 8.44 State diagram for the Moore-type serial adder FSM

slide54
Nextstate

Present

Nextstate

Present

Output

Output

ab

state

=00

01

10

11

state

ab

=00

01

10

11

s

y

y

s

2

1

Y

Y

2

1

G

G

G

G

H

0

0

0

1

1

0

00

0

0

01

0

1

10

0

G

G

G

G

H

1

1

0

1

1

0

01

0

0

01

0

1

10

1

H

G

H

H

H

0

0

1

0

0

1

10

0

1

10

1

0

11

0

H

G

H

H

H

1

1

1

0

0

1

11

0

1

10

1

0

11

1

Figure 8.45 State table for the Moore-type serial adder FSM

slide55
y

Y

Sum bit

1

1

a

s

Q

D

Full

b

adder

Carry-out

Q

Y

y

2

2

Q

D

Clock

Q

Reset

Figure 8.47 Circuit for the Moore-type serial adder FSM

slide56
LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

-- left-to-right shift register with parallel load and enable

ENTITY shiftrne IS

GENERIC ( N : INTEGER := 4 ) ;

PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

L, E, w : IN STD_LOGIC ;

Clock : IN STD_LOGIC ;

Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END shiftrne ;

ARCHITECTURE Behavior OF shiftrne IS

BEGIN

PROCESS

BEGIN

… con’t

Figure 8.48a Code for a left-to-right shift register with an enable input

slide57
WAIT UNTIL Clock'EVENT AND Clock = '1' ;

IF E = '1' THEN

IF L = '1' THEN

Q <= R ;

ELSE

Genbits: FOR i IN 0 TO N-2 LOOP

Q(i) <= Q(i+1) ;

END LOOP ;

Q(N-1) <= w ;

END IF ;

END IF ;

END PROCESS ;

END Behavior ;

Figure 8.48b Code for a left-to-right shift register with an enable input (con’t)

slide58
LIBRARY ieee ;

USE ieee.std_logic_1164.all ;

ENTITY serial IS

GENERIC ( length : INTEGER := 8 ) ;

PORT ( Clock : IN STD_LOGIC ;

Reset : IN STD_LOGIC ;

A, B : IN STD_LOGIC_VECTOR(length-1 DOWNTO 0) ;

Sum : BUFFER STD_LOGIC_VECTOR(length-1 DOWNTO 0) );

END serial ;

ARCHITECTURE Behavior OF serial IS

COMPONENT shiftrne

GENERIC ( N : INTEGER := 4 ) ;

PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;

L, E, w : IN STD_LOGIC ;

Clock : IN STD_LOGIC ;

Q : BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;

END COMPONENT ;

SIGNAL QA, QB, Null_in : STD_LOGIC_VECTOR(length-1 DOWNTO 0) ;

SIGNAL s, Low, High, Run : STD_LOGIC ;

SIGNAL Count : INTEGER RANGE 0 TO length ;

TYPE State_type IS (G, H) ;

SIGNAL y : State_type ;

… con’t

Figure 8.49a VHDL code for the serial adder

slide59
BEGIN

Low <= '0' ; High <= '1' ;

ShiftA: shiftrne GENERIC MAP (N => length)

PORT MAP ( A, Reset, High, Low, Clock, QA ) ;

ShiftB: shiftrne GENERIC MAP (N => length)

PORT MAP ( B, Reset, High, Low, Clock, QB ) ;

AdderFSM: PROCESS ( Reset, Clock )

BEGIN

IF Reset = '1' THEN

y <= G ;

ELSIF Clock'EVENT AND Clock = '1' THEN

CASE y IS

WHEN G =>

IF QA(0) = '1' AND QB(0) = '1' THEN y <= H ;

ELSE y <= G ;

END IF ;

WHEN H =>

IF QA(0) = '0' AND QB(0) = '0' THEN y <= G ;

ELSE y <= H ;

END IF ;

END CASE ;

END IF ;

END PROCESS AdderFSM ;

… con’t

Figure 8.49b VHDL code for the serial adder (con’t)

slide60
WITH y SELECT

s <= QA(0) XOR QB(0) WHEN G,

NOT ( QA(0) XOR QB(0) ) WHEN H ;

Null_in <= (OTHERS => '0') ;

ShiftSum: shiftrne GENERIC MAP ( N => length )

PORT MAP ( Null_in, Reset, Run, s, Clock, Sum ) ;

Stop: PROCESS

BEGIN

WAIT UNTIL (Clock'EVENT AND Clock = '1') ;

IF Reset = '1' THEN

Count <= length ;

ELSIF Run = '1' THEN

Count <= Count -1 ;

END IF ;

END PROCESS ;

Run <= '0' WHEN Count = 0 ELSE '1' ; -- stops counter and ShiftSum

END Behavior ;

Figure 8.49c VHDL code for the serial adder (con’t)

slide61
1

0

0

0

a

a

D

D

D

D

7

0

3

2

1

0

L

Counter

E

L

w

0

Q

Q

Q

Q

3

2

1

0

1

E

Adder

b

b

FSM

7

0

Run

L

0

0

w

0

1

E

L

w

E

Clock

Reset

Sum

Sum

7

0

Figure 8.50a Synthesized serial adder

state minimization
State Minimization
  • It is often difficult for designer to find FSM with minimal number of states.
  • Fewer states leads to fewer flip-flops.
  • Two states Si and Sj are equivalent iff for every input sequence starting in Sior Sj, the same output sequence is produced.
partitioning minimization
Partitioning Minimization
  • If w=0 in Si and result is Su then Su is 0-successor.
  • If w=1 in Si and result is Sv then Sv is 1-successor.
  • Si and Sj are equivalent if k-successors equivalent.
  • Consider states as set then break set into partitions comprised of subsets which are not equivalent.
  • A partition consists of 1 or more blocks, each block comprises a subset of states that may be equivalent, but states in a block are definitely not equivalent to states in another block.
slide65
Next state

Present

Output

z

state

w

=

0

w

=

1

A

B

C

1

B

D

F

1

C

F

E

0

D

B

G

1

E

F

C

0

F

E

D

0

G

F

G

0

Figure 8.51 State table for Example 8.5

slide66
Nextstate

Present

Output

z

state

w

=

0

w

=

1

A

B

C

1

B

A

F

1

C

F

C

0

F

C

A

0

Figure 8.52 Minimized state table for Example 8.5

slide67
Clock

sense

N

sense

D

N

D

(a) Timing diagram

N

sense

Q

Q

D

D

N

Clock

Q

Q

N

(b) Circuit that generates

Figure 8.53 Signals for the vending machine

slide68
DN

Reset

DN

¤

S1

0

DN

DN

DN

DN

D

N

D

¤

¤

S2

0

S3

0

¤

¤

S4

1

S7

1

N

D

N

DN

¤

S6

0

¤

S5

1

DN

DN

N

D

¤

¤

S8

1

S9

1

Figure 8.54 State diagram for Example 8.6

slide69
Next state

Present

Output

state

z

DN

=00

01

10

11

S1

S1

S3

S2

0

S2

S2

S4

S5

0

S3

S3

S6

S7

0

S4

S1

1

S5

S3

1

S6

S6

S8

S9

0

S7

S1

1

S8

S1

1

S9

S3

1

Figure 8.55 State table for Example 8.6

slide70
Next state

Present

Output

state

z

DN

=00

01

10

11

S1

S1

S3

S2

0

S2

S2

S4

S5

0

S3

S3

S2

S4

0

S4

S1

1

S5

S3

1

Figure 8.56 Minimized state table for Example 8.6

slide71
DN

¤

S1

0

N

DN

¤

S3

0

D

DN

DN

N

D

¤

¤

S2

0

S5

1

DN

N

D

¤

S4

1

Figure 8.57 Minimized state diagram for Example 8.6

slide72
¤

DN

0

S1

¤

¤

N

0

D

1

¤

DN

0

S3

¤

¤

N

1

D

0

¤

¤

N

0

D

1

S2

¤

DN

0

Figure 8.58 Mealy-type FSM for Example 8.6

incompletely specified fsms
Incompletely Specified FSMs
  • Partitioning scheme works well when all entries in state table are specified.
  • If one or more entries are not specified, then the FSM is incompletely specified.
  • Partitioning scheme not guaranteed to produce minimal solution in this case.
slide74
z

Next state

Output

Present

state

w

=

0

w

=

1

w

=

0

w

=

1

A

B

C

0

0

B

D

0

C

F

E

0

1

D

B

G

0

0

E

F

C

0

1

F

E

D

0

1

G

F

0

Figure 8.59 Incompletely specified state table for Example 8.7

slide75
z

Next state

Output

Present

state

w

=

0

w

=

1

w

=

0

w

=

1

A

B

C

0

0

B

D

0

C

F

E

0

1

D

B

G

0

0

E

F

C

0

1

F

E

D

0

1

G

F

0

Figure 8.59 Incompletely specified state table for Example 8.7

slide76
=

0

=

0

=

0

w

w

w

=

0

w

=

1

=

1

=

1

w

w

w

A/0

B/1

C/2

D/3

=

1

=

1

w

w

H/7

G/6

F/5

E/4

=

1

=

1

=

1

w

w

w

=

0

=

0

=

0

=

0

w

w

w

w

Figure 8.60 State diagram for a counter

slide77
Next state

Present

Output

state

w

=

0

w

=

1

A

A

B

0

B

B

C

1

C

C

D

2

D

D

E

3

E

E

F

4

F

F

G

5

G

G

H

6

H

H

A

7

Figure 8.61 State table for the counter

slide78
Next state

Present

Count

state

w

=

0

w

=

1

y

y

y

z

z

z

2

1

0

2

1

0

Y

Y

Y

Y

Y

Y

2

1

0

2

1

0

A

000

000

001

000

B

001

001

010

001

C

010

010

011

010

D

011

011

100

011

E

100

100

101

100

F

101

101

110

101

G

110

110

111

110

H

111

111

000

111

Figure 8.62 State-assigned table for the counter

slide79
y

y

y

y

1

0

1

0

wy

wy

2

2

00

01

11

10

00

01

11

10

00

00

0

1

1

0

0

0

1

1

01

01

0

1

1

0

0

0

1

1

11

1

0

0

1

11

0

1

0

1

10

1

0

0

1

10

0

1

0

1

Y

=

wy

+

wy

Y

=

wy

+

y

y

+

wy

y

0

0

0

0

1

1

1

0

1

y

y

1

0

wy

2

00

01

11

10

00

0

0

0

0

01

1

1

1

1

11

1

1

0

1

10

0

0

1

0

Y

=

wy

+

y

y

+

y

y

+

w

y

y

y

0

1

2

2

2

2

2

0

1

Figure 8.63 Karnaugh maps for D flip-flops for the counter

slide80
w

Y

0

y

Q

D

0

Q

Y

1

y

Q

D

1

Q

Y

2

y

Q

D

2

Q

Clock

Resetn

Figure 8.64 Circuit diagram for the counter

implementation using jk ff
Implementation Using JK-FF
  • If FF in state 0 to remain 0, J=0 and K=d.
  • If FF in state 0 to change to 1, J=1 and K=d.
  • If FF in state 1 to remain 1, J=d and K=0.
  • If FF in state 1 to change to 0, J=d and K=1.
slide82
Flip-flop inputs

Present

Count

w

=

0

w

=

1

state

y

y

y

z

z

z

2

1

0

2

1

0

Y

Y

Y

J

K

J

K

J

K

Y

Y

Y

J

K

J

K

J

K

2

1

0

2

2

1

1

0

0

2

1

0

2

2

1

1

0

0

000

000

0d

0d

0d

001

0d

0d

1d

000

A

001

001

0d

0d

d0

010

0d

1d

d1

001

B

010

010

0d

d0

0d

011

0d

d0

1d

010

C

011

011

0d

d0

d0

100

1d

d1

d1

011

D

100

100

d0

0d

0d

101

d0

0d

1d

100

E

101

101

d0

0d

d0

110

d0

1d

d1

101

F

110

110

d0

d0

0d

111

d0

d0

1d

110

G

111

111

d0

d0

d0

000

d1

d1

d1

111

H

Figure 8.65 Excitation table for the counter with JK flip-flops

slide83
y

y

y

y

1

0

1

0

wy

wy

2

2

00

01

11

10

00

01

11

10

00

00

0

d

d

0

d

0

0

d

01

01

0

d

d

0

d

0

0

d

11

1

d

d

1

11

d

1

1

d

10

1

d

d

1

10

d

1

1

d

=

=

J

w

K

w

0

0

y

y

y

y

1

0

1

0

wy

wy

2

2

00

01

11

10

00

01

11

10

00

00

0

0

d

d

d

d

0

0

01

01

0

0

d

d

d

d

0

0

11

0

1

d

d

11

d

d

1

0

10

0

1

d

d

10

d

d

1

0

=

=

J

wy

K

wy

1

0

1

0

y

y

y

y

1

0

1

0

wy

wy

2

2

00

01

11

10

00

01

11

10

00

00

0

0

0

0

d

d

d

d

01

01

d

d

d

d

0

0

0

0

11

d

d

d

d

11

0

0

1

0

10

0

0

1

0

10

d

d

d

d

=

=

J

wy

y

K

wy

y

2

0

1

2

0

1

Figure 8.66 Circuit diagram for the counter

slide86
Present

Next

Output

z

z

z

state

state

2

1

0

A

B

000

B

C

100

C

D

010

D

E

110

E

F

001

F

G

101

G

H

011

H

A

111

Figure 8.69 State table for the counterlike example

slide87
Present

Next

Output

state

state

y

y

y

Y

Y

Y

z

z

z

2

1

0

2

1

0

2

1

0

000

1

00

0

00

100

0

10

1

00

010

1

10

0

10

110

0

01

1

10

001

1

01

0

01

101

0

11

1

01

011

1

11

0

11

111

0

00

1

11

Figure 8.70 State-assigned table

slide88
z

Q

D

2

Q

z

Q

D

1

Q

z

Q

D

0

w

Q

Figure 8.71 Circuit for the counterlike example

slide89
000

Reset

Idle

0xx

1xx

¤

gnt1

g

=

1

1

1xx

x0x

01x

¤

gnt2

g

=

1

2

x1x

xx0

001

¤

gnt3

g

=

1

3

xx1

Figure 8.72 State diagram for the arbiter

slide90
r

r

r

1

2

3

Reset

Idle

r

r

1

1

¤

gnt1

g

=

1

1

r

r

r

r

1

2

1

2

¤

gnt2

g

=

1

2

r

r

r

r

r

2

3

1

2

3

¤

gnt3

g

=

1

3

r

3

Figure 8.73 Alternative style of state diagram for the arbiter

slide91
LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY arbiter IS

PORT ( Clock, Resetn : IN STD_LOGIC ;

r : IN STD_LOGIC_VECTOR(1 TO 3) ;

g : OUT STD_LOGIC_VECTOR(1 TO 3) ) ;

END arbiter ;

ARCHITECTURE Behavior OF arbiter IS

TYPE State_type IS (Idle, gnt1, gnt2, gnt3) ;

SIGNAL y : State_type ;

BEGIN

PROCESS ( Resetn, Clock )

BEGIN

IF Resetn = '0' THEN y <= Idle ;

ELSIF (Clock'EVENT AND Clock = '1') THEN

CASE y IS

WHEN Idle =>

IF r(1) = '1' THEN y <= gnt1 ;

ELSIF r(2) = '1' THEN y <= gnt2 ;

ELSIF r(3) = '1' THEN y <= gnt3 ;

ELSE y <= Idle ;

END IF ;

… con’t

Figure 8.74a VHDL code for the arbiter

slide92
WHEN gnt1 =>

IF r(1) = '1' THEN y <= gnt1 ;

ELSE y <= Idle ;

END IF ;

WHEN gnt2 =>

IF r(2) = '1' THEN y <= gnt2 ;

ELSE y <= Idle ;

END IF ;

WHEN gnt3 =>

IF r(3) = '1' THEN y <= gnt3 ;

ELSE y <= Idle ;

END IF ;

END CASE ;

END IF ;

END PROCESS ;

g(1) <= '1' WHEN y = gnt1 ELSE '0' ;

g(2) <= '1' WHEN y = gnt2 ELSE '0' ;

g(3) <= '1' WHEN y = gnt3 ELSE '0' ;

END Behavior ;

Figure 8.74b VHDL code for the arbiter (con’t)

slide93
.

.

.

PROCESS( y )

BEGIN

IF y = gnt1 THEN g(1) <= '1' ;

ELSIF y = gnt2 THEN g(2) <= '1' ;

ELSIF y = gnt3 THEN g(3) <= '1' ;

END IF ;

END PROCESS ;

END Behavior ;

Figure 8.75 Incorrect VHDL code for the grant signals

slide94
.

.

.

PROCESS( y )

BEGIN

g(1) <= '0' ;

g(2) <= '0' ;

g(3) <= '0' ;

IF y = gnt1 THEN g(1) <= '1' ;

ELSIF y = gnt2 THEN g(2) <= '1' ;

ELSIF y = gnt3 THEN g(3) <= '1' ;

END IF ;

END PROCESS ;

END Behavior ;

Figure 8.76 Correct VHDL code for the grant signals

slide96
a) Output delays using binary encoding

b) Output delays using one-hot encoding

Figure 8.78 Output delays in the arbiter circuit

slide98
Next State

Present

Output

Next state

state

w

=

0

w

=

1

Present

Output

z

y

y

state

z

2

1

Y

Y

Y

Y

w

=

0

w

=

1

2

1

2

1

0

0

0

0

01

0

A

A

B

0

0

1

0

0

10

0

B

A

C

0

1

0

0

0

11

0

C

A

D

0

1

1

0

0

11

1

D

A

D

1

(a)State-assigned table

(b)State table

Figure 8.81 Tables for the circuit in Example 8.8

slide99
y

J

1

1

w

Q

J

z

K

Q

K

1

y

J

2

2

Q

J

Clock

K

Q

K

2

Resetn

Figure 8.82 Circuit for Example 8.9

slide100
Flip-flop inputs

Present

Output

state

w

=

0

w

=

1

y

y

z

2

1

J

K

J

K

J

K

J

K

2

2

1

1

2

2

1

1

00

01

0

1

0

0

1

1

0

01

01

0

1

1

0

1

1

0

10

01

0

1

0

0

1

0

0

11

01

0

1

1

0

1

0

1

Figure 8.83 Excitation table

slide102
Flip-flop inputs

Present

Output

w

=

0

w

=

1

state

z

y

y

2

1

T

D

T

D

2

1

2

1

0

0

0

0

01

0

0

1

0

0

10

0

1

0

1

0

01

0

1

1

1

0

01

1

Figure 8.85 Excitation table

slide103
State name

Output signals

0 (False)

1 (True)

Condition

or actions

expression

(Moore type)

(a) State box

(b) Decision box

Conditional outputs

or actions (Mealy type)

(c) Conditional output box

Figure 8.86 Elements used in ASM charts

slide104
Reset

A

0

w

1

B

0

w

1

C

z

0

1

w

Figure 8.87 ASM chart for a simple FSM

slide106
Reset

Idle

1

r

1

gnt1

1

0

0

g

1

r

1

1

r

2

1

0

gnt2

0

g

2

r

2

0

1

r

3

1

gnt3

0

g

3

r

3

Figure 8.89 ASM chart for the arbiter

slide107
w

z

1

1

Outputs

Inputs

Combinational

w

z

n

m

circuit

y

Y

k

k

Next-state

Present-state

variables

variables

y

Y

1

1

Figure 8.90 The general model for a sequential circuit

formal model for fsms
Formal Model for FSMs
  • M = (W, Z, S, , )
    • W is finite, nonempty set of inputs.
    • Z is finite, nonempty set of outputs.
    • S is finite, nonempty set of states.
    •  is the state transition function:
      • S(t+1) = [W(t),S(t)]
    •  is the output function:
      • (t) = [S(t)] (Moore model)
      • (t) = [W(t),S(t)] (Mealy model)
summary
Summary
  • FSM Design (Moore and Mealy)
    • State minimization
    • State assignment
    • Using CAD tools and VHDL
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