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Integrating SLC/EPICS Timing for Control System Efficiency

This document outlines the motivation, key components, and status update for integrating SLC/EPICS timing. It discusses the benefits of using EPICS platform for a pulsar LINAC application and provides details on the software and hardware tasks involved. Conclusions and recommendations are also included.

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Integrating SLC/EPICS Timing for Control System Efficiency

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  1. SLC IntegrationLCLS Facility Advisory Committee April 29-30, 2004 • Outline • Motivation • Key Components • Status Update • SLC / EPICS Timing • Software Tasks • Hardware Tasks • Conclusions

  2. Motivation for Integrating SLC / EPICS • Many of the SLC high level applications running on the SLC control system are required for commissioning and operation. • Sectors 20-30 of the existing SLC LINAC will be used with minimal modifications. The LINAC is instrumented and the data is in the SLC control system. • No budget or schedule to replace the first two items. • The SLC technology is dated and an upgrade path is highly desirable. • EPICS provides a platform that is widely used that supports the requirements of a pulsed LINAC.

  3. Key Components of SLC / EPICS Integration • Timing System Integration • Support integration to the RF based timing • Provide Beam Code and User Code information to EPICS environment • Create an SLC-Aware IOC that can emulate the SLC Micro functions in an EPICS IOC, making all EPICS data available to existing SLC high level applications. • Build on the EPICS Server that provides SLC data to an EPICS environment to provide existing SLC data in the LINAC for high level applications in the EPICS environment.

  4. Update: February 2004 – April 2004 • Prior to February 2004 a timing integration meeting was held at SLAC to consider using the SLC timing front-end with an EPICS timing system. (PSI was considered) • Design changed to include SLC-aware IOC • Allowed new designs outside of CAMAC • Caused extensive re-costing throughout the WBS • Three design discussion meetings have been held to discuss SLC/EPICS integration • An SLC expert, Tony Gromme, has provided significant detailed information to support the understanding of the effort

  5. Integrating SLC and EPICS Timing Nsec resolution on the timing gates produced from the Event Rcvr 50 psec jitter pulse to pulse Event generator passes along beam code data from SLC Event generator sends events to receivers including: 360 Hz, 120 Hz, 10 Hz and 1 Hz fiducials last beam pulse OK Machine mode EPICS time stamp Event receivers produce to the IOC interrupts on events data from the event generator in registers 16 triggers with configurable delay and width 476 MHz RF Reference SLC micro Master Pattern Generator PNET (128 bit beam Code @ 360 Hz) FIDO 119 MHz w/ 360 Hz fiducial Vacuum Ctrl E VG P N E T R C V R EVR Power Supply Ctrl C P U EVR LLRF (digitzer) EVR Diag C P U C P U C P U IOC IOC IOC 16 triggers 16 triggers Drive Laser Off Machine Protection Beam Code + EPICS Time + EPICS Events

  6. SLC Net “Micro” Communication Provides data to SLC Applications from EPICS Operates at 10 Hz (not beam synched) Requires significant development in the IOC to emulate SLC “micro” in the IOC On an application by application basis we will evaluate what functions to provide SLC Alpha Apps Xterm Xterm Xterm Xterm SLC-Net over Ethernet Vacuum Ctrl E VG P N E T R C V R EVR Pwr Supply Ctrl C P U EVR LLRF (digitzer) EVR Diag C P U C P U C P U IOC IOC IOC

  7. SLC to EPICS Communication EPICS W/S Distributed Applications EPICS W/S Distributed Applications SLC Alpha Apps EPICS W/S Distributed Applications Xterm Xterm EPICS W/S Distributed Applications Xterm EPICS WS Distributed High Level Applications Xterm Channel Access Vacuum Ctrl E VG P N E T R C V R EVR Power Supply Ctrl C P U EVR LLRF (digitizer) EVR Diag C P U C P U C P U IOC IOC IOC A channel access server in SLC provides data from existing SLC micros to EPICS applications All IOCs have both a channel access server to allow access and a client to have access Channel access provides read/write by all clients to all data with a server. All EPICS high level applications are channel access clients that may or may not have a server.

  8. Final Architecture – Incl. Feedback and MPS EPICS W/S Distributed Applications EPICS W/S Distributed Applications SLC Alpha Apps EPICS W/S Distributed Applications Xterm Xterm EPICS W/S Distributed Applications Xterm EPICS WS Distributed High Level Applications Xterm Fast Feedback over Ethernet? SLC-Net over Ethernet Channel Access Vacuum Ctrl E VG P N E T R C V R EVR Pwr Supply Ctrl C P U EVR LLRF EVR Diag C P U HPRF I/O Boards C P U C P U IOC IOC IOC 16 triggers 16 triggers Beam Stop In Drive Laser Off Machine Protection Beam Code + EPICS Time + EPICS Events

  9. SLC Aware Software Development • Determine on an application-by-application basis if it is better to replicate the SLC micro communication capability or move the application into EPICS • Straight through beam is needed 2 months per year • Upfront effort and maintainability are the key factors • Timing integration required early • Decode 128 bit SLC beam code at 360 Hz into EPICS • Provide a master pattern generator • SLC communication tasks will be implemented one at a time, starting with the database exchange (dbex) • Synchronous and buffered acquisition is required • Is KIS-net required for straight through beam?

  10. SLC Aware Hardware Development • Timing integration required early • Decode 128 bit SLC beam code at 360 Hz into EPICS • Maintain 20 psec jitter and provide 1 nsec gate resolution • All new board designs depend on the ability to integrate timing hardware and SLC software • Hardware designs that are dependent on this approach include: • Low Level RF • Beam Position Monitors & all other diagnostics • Power Supply Controls • Image Capture • Motion Controls

  11. Conclusions • Our key risk is in the design of an SLC-aware IOC and SLC to EPICS timing that will allow us to intermix the SLC and EPICS front-ends. • This approach provides an incremental upgrade path for the SLC Linac. • Expert support from ESD makes this design possible. • Early prototypes are required to demonstrate this approach and provide platforms for the development of other subsystems such as LLRF, BPMs and Power Supply Control.

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