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Methodology for effective hierarchical verification of low power designs. Ramesh Rajagopalan ( firstname.lastname@example.org ), Cisco Systems Inc, San Jose, CA Namit Gupta ( email@example.com ), Synopsys Inc, Mountain View , CA. Authors Information.
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Ramesh Rajagopalan (firstname.lastname@example.org), Cisco Systems Inc, San Jose, CA
Namit Gupta (email@example.com), Synopsys Inc, Mountain View , CA
1)Ramesh Rajagopalan ,Cisco Systems Inc, firstname.lastname@example.org,
Ramesh has been in the physical design field for over 19 years and he is currently a Technical Leader with Switching Silicon Group at Cisco. Physical design of Custom network switching ASICs and UltraSparc microprocessors form part of his experience.
2) Namit Gupta, Synopsys Inc,
Namit Gupta is a Staff corporate application engineer at Synopsys Inc with responsibility for verification solutions. Gupta holds a bachelor’s degree in electronics from the Indian Institute of Technology, Delhi. Among Gupta’s interest areas are RTL design and verification, clock domain crossing, low power, design constraints, and ESL.
Phone 550-215-0765 Email email@example.com
Current size and complexity of SOC/ASIC designs dictate
- use of advanced low power techniques to reduce power and
- saving and restoring of critical design states.
Use of multiple voltages in the design is one of the widely adopted low power technique.
- Different parts of a chip might have different speed requirements.
- A lower supply voltage reduces power consumption but also reduces speed.
- To get maximum speed and lower power at the same time, only blocks that need to work at higher clock rates can operate with a higher supply voltage while the other blocks can operate with a lower voltage.
Figure 1: Example of PST merging with disjoint set of supply signals
Figure 2: PST Example of PST merging overlapping set of supply signals
PST verification is a very critical step and we need to fine tune the methodology to make it of signoff quality.