Lecture # 2 Low Power CMOS Design Source: Eby G. Friedman University of Rochester

1. Lecture # 2 Low Power CMOS Design Source: Eby G. Friedman University of Rochester

2. Low Power CMOS Circuit Design Two reasons for low power • Battery operation - draining the charge • Instantaneous power producing power density problems • Affecting packaging and cooling strategies  cost • Hot spots also degrade delay in critical paths PDYN = pt• CL • VDD2• fCLK PLEAK = K • 10-Vth/S•VDD PT - switching probability S - subthreshold slope ~ 0.1 volts/decade - velocity saturation affect ~ 1.4, 1 <  < 2 K = ƒ (circuit, layout, and device parameters)

3. Power Dissipation • Has increased due to • Higher clock frequencies • Denser integration • Components of power dissipation • Dynamic • Short circuit • Leakage • Dynamic component due to charge/discharge capacitance • Gate • Interconnect • Diffusion

4. Dynamic Power in a Modern Microprocessor Interconnect dynamic power is more than half !!

5. General Approach to Low Power Design: Dynamic Component PDYN = Pt • CL • VDD2 fCLK • Lower VDD • Most attractive due to quadratic dependence • However, TPD • Reduce CL • Lower Pt

6. General Approach to Low Power Design: Leakage Component PLEAK = K • 10Vth/S•VDD • Greater Vth • Most attractive due to exponential dependence • However, TPD • Reduce transistor size (K) • Reduce power supply voltage VDD

7. Single Supply Voltage CMOS Excessive slack Tnon-critical = Tclock – (Tsafety-margin + Tidle) Critical Path Tcritical = Tclock – Tsafety-margin • Clock speed • Delay of the most critical paths • Supply voltage • To satisfy the target clock frequency along the critical paths • Gates on non-critical paths operate with excessive slack • Same supply voltage on critical and non-critical delay paths wastes energy

8. Multiple Supply Voltage CMOS Low VDD Critical Path High VDD • Exploit excessive slack on non-critical delay paths • Selectively lower the supply voltage on the non-critical paths • No performance degradation as compared to a single supply voltage circuit • Significant power reduction

9. Threshold Voltage Scaling 100 |Vt| = 0.5 V |V | = 0.5 V t |Vt| = 0.4 V |Vt| = 0.3 V |Vt| = 0.2 V |Vt| = 0.1 V |Vt| = 0.02 V Delay (ps) |Vt | = 0.02 t Equal-delay line 10 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VDD (V) • Enhances circuit speed • Increases gate overdrive |VGS| - |Vt|

10. Subthreshold Leakage Current 900 Total Power 800 Subthreshold Leakage 700 600 500 Power (Watts) 400 300 200 100 0 1998 2000 2002 2004 2006 2008 2010 Year • Primary source of energy dissipation in an idle circuit • Reduces the battery lifetime in portable applications • Significant contributor to active mode power • Aggressive scaling

11. Techniques for Low Voltage Design Lower VDD • To maintain chip throughput • Lower VTH to recover circuit speed • Employ dual-VTprocess and use lower VT for critical circuits • Employ multiple supply voltage and use lower VDD for non-critical circuits • Utilize parallel and/or pipeline architectures to compensate for degraded circuit speed

12. Low Power Design Issues • Dynamic supply voltage scaling • Multi-threshold voltage CMOS • Near threshold computing • Low swing interconnect • Adaptive body biasing • Architecture-based voltage scaling • Arithmetic transformations • Low leakage design techniques 

13. Dynamic Supply Voltage Scaling Computation intensive and short - latency processes Maximum Processor Speed Required Throughput (MIPS) time Background and long - latency processes System idle • Computational load varies with time • Peak performance requirements followed by idle periods • Battery lifetime in portable devices • Tidle >> Tactive

14. Dynamic Supply Voltage Scaling (DVS) Ring Oscillator VDD2 f1MHz fCLOCK Reset Counter Microprocessor VDD1 fMEASURED P1 fDESIRED fERROR 0110100 Filter Inductor Regular MOSFET gate drivers Filter Capacitor N1 Digital Loop Filter • Exploits variations in computational workload • Dynamically modify the supply voltage and clock frequency • Provide high throughput only when necessary • Save energy for the rest of the time • For low throughput applications, lower the supply voltage together with the clock frequency

15. Low Voltage Design Issues • Dynamic supply voltage scaling • Multi-threshold voltage scaling • Near threshold computing • Low swing interconnect • Adaptive body biasing • Architecture-based voltage scaling • Arithmetic transformations • Low leakage design techniques 

16. Multiple Threshold Voltage CMOS Excessive slack T = T – ( T + T ) non -critical clock safety -margin idle High Threshold Voltage Transistors Critical Path Low Threshold Voltage (Leaky) Transistors • Exploit excessive slack along non-critical delay paths • Same low threshold voltages on the critical and non-critical delay paths wastes energy • Selectively lower the threshold voltages only along the critical paths • No performance degradation • Significant leakage power reduction • Minimizes the number of low-Vt transistors • Maximizes the number of high-Vt transistors

17. Combination of Multiple VDD and VT • Multiple supply and threshold voltage CMOS • Along the non-critical delay paths • Further scaling the supply voltage • Along the speed critical paths • Further scaling the threshold voltage • Dynamic supply and threshold voltage scaling • Trades subthreshold leakage power with dynamic switching power • Optimize to minimize the total power • Optimized VDD and VTH is essential for low power, high speed CMOS circuits

18. Design Issues at Low Level VDD and Low VTH Advantage • High speed, low power CMOS circuit operation Disadvantages • Increased standby power dissipation in low VT • Inability to sort out defective chips by monitoring quiescent power supply current • IDDQ testing • Greater dependence on VTH variations • Degrades speed in critical paths • Standby power is important in portable equipment and microprocessors • Issue becomes how best to control VTH • Difficult to achieve through process and device refinement Two approaches to control VTH • Doping levels during manufacturing process • Controlling VTH through substrate bias Power-down schemes • An approach to cut leakage current and save battery life • Microprocessors are in standby mode most of the time

19. Low Voltage Design Issues • Dynamic supply voltage scaling • Multi-threshold voltage scaling • Near threshold computing • Low swing interconnect • Adaptive body biasing • Architecture-based voltage scaling • Arithmetic transformations • Low leakage design techniques 

20. The Two Extremes • Subthreshold region • Low speed • Low energy per operation • Super threshold region • High speed • High energy per operation • 20

21. A Balanced Approach • Near threshold region • Balanced delay and energy per operation • 2x energy increasevs. sub-Vth • 10x speed reduction vs. super-Vth • 21

22. Near Threshold Circuits (NTC) Market • Handheld devices • Battery life and size • Processing speed is not a major constraint • Portable computers • Low power operation mode • Multi-core processors • Using 10 to 100 NTC cores will regain speed loss • Maintain low power consumption • Improve system responsiveness • 22

23. Level Shifter Circuit for NTC V Vhigh Vout VNTC Vin Vlow t

24. Low Power Design Issues • Dynamic supply voltage scaling • Multi-threshold voltage CMOS • Near threshold computing • Low swing interconnect • Adaptive body biasing • Architecture-based voltage scaling • Arithmetic transformations • Low leakage design techniques 

25. Multiple Supply Voltages V V V DD1 DD3 DD2 Circuit Circuit Circuit Swing Swing Block Block 1 2 Block 3 1 • Different circuit blocks operate at different voltage levels • Specialized voltage interface circuits are necessary

26. Multiple Supply Voltages VDD1 VDD2 VDD2 P P VDD1 0 0 Node1 Node2 Istatic • Static DC Power • Degraded output voltage swing • Low speed signal transfer • VDD2 < VDD1 • Specialized voltage interface circuits are necessary • High speed and energy efficient signaling

27. Multiple Supply Voltages • Reduced voltage swing logic on output node • Using NMOS pull-up reduces Vhigh = VD – VT P = CLVDD (VDD – VT)ƒ Disadvantages • NMH is reduced by VT • P-channel of next stage can be turned on all the time • Therefore, use special gates to restore noise margin and eliminate ISC • Added capacitance • Particularly appropriate for long interconnect lines • Could use differential signaling across entire length of the line • Large overhead to convert voltages • Only useful in highly capacitive lines • Need low voltage DC-to-DC converters

28. Low Swing Interconnect Swing 1 Swing 2 Swing 1 Interconnect Circuit Block Circuit Block Driver Receiver • Voltage level converters are required • Driver end • Reduce the voltage swing • Receiver end • Regenerate the high voltage level required by the circuit blocks • Specialized voltage interface circuits are necessary • High speed and energy efficient signal transfer

29. Low Power Voltage Interface Circuit VDD2 VDD1 P2 P1 P2 P3 P4 Node4 Node 2 I2 N2 Node 3 N1 Output Input I3 I2 N3 Node 1 • No static DC current • Full output voltage swing • 0 to VDD2 • VDD2 < VDD1

30. Low Power Voltage Interface Circuit 8 CQ 7 SF ZGR 6 NIITA KSF 5 Average Delay, ns 4 3 2 1 0 0 5 10 15 CL , pF • Lower power, enhanced performance, and small area as compared to previously published circuits • 1.8 volts to 3.3 volts • 0.18 um CMOS technology • Up to 3.6x delay improvement • Up to 198x power reduction Proposed circuit

31. High Energy Efficiency 100 80 60 Level Converter Efficiency 40 CQ SF 20 ZGR NIITA KSF 0 0 5 10 15 CL (pF) • 89% to 99% level conversion efficiency • CL = 1 pF to 15 pF

32. High Energy Efficiency Proposed circuit • Critical for light loads • Low power systems with multiple supply voltages • Minimize the energy overhead • CL = 1 pF

33. Experimental Results VDD2 = 5 V VDD2 = 10 V VDD1 = 10 V VDD1 = 5 V • 5 volts to 10 volts interface • Circuit operation verified by experimental test circuits

34. Low Power Design Issues • Dynamic supply voltage scaling • Multi-threshold voltage CMOS • Near threshold computing • Low swing interconnect • Adaptive body biasing • Architecture-based voltage scaling • Arithmetic transformations • Low leakage design techniques 

35. Controlling VTH Through the Substrate Bias VDD VBBP P N N - channel VBBN P - channel. Body effect As increased VSB, the channel–to–substrate depletion layer increases, resulting in increased density of trapped carriers in the depletion region 0.4 < < 1.2 V1/2 VT = VT(0)+ (VSB)1/2 • A transistor is treated as a four terminal device rather than as a three terminal device • Now possible to control VT at the circuit level • VTCMOS = CMOS with variable VT • Reverse body bias (RBB) = VSB > 0 for NMOS • Reduced leakage • Lower performance • Forward body bias (FBB) = VSB < 0 for NMOS • Higher performance • Increased leakage • Improvement in short channel effects • VT variations are compensated by feedback controlling the substrate bias VBB using an on-chip self-substrate bias circuit (SSB) and a leakage current monitor (LCM) • The monitored leakage current is set to a target value

36. Adaptive Body Biasing for Process Variations Measured leakage power and frequency for 62 dies • Forward body bias for dies that are too slow • Reverse body bias for dies that violate the leakage constraint • Single NMOS and PMOS body bias combination per die maximizing the die frequency while meeting leakage constraint • Requires body bias generator and control circuitry J. W. Tschanz et al., IEEE Journal of Solid-State Circuits, November 2002.

37. Low Power Design Issues • Dynamic supply voltage scaling • Multi-threshold voltage CMOS • Near threshold computing • Low swing interconnect • Adaptive body biasing • Architecture-based voltage scaling • Arithmetic transformations • Low leakage design techniques 

38. Architecture-Based Voltage Scaling Strategy Adder A Comparator Pref = Cref V2refƒref a>b VDD =5V B C A 8-bit adder 8-bit adder B A) Simple 8-bit data path B) Use parallel architecture to reduce VDD while maintaining speed ƒpar = 1/2 ƒref Vpar  2.9V to maintain speed Cpar = 2 Cref and extra routing = 2.15 Cref Ppar = CparVpar2ƒpar= (2.15 Cref) (0.58Vref) 2 • Parallelism can be further increased • However, TPD  with VDD ≈ 0.36 Pref

39. Architecture-Based Voltage Scaling Strategy Adder A Comparator B Architecture Voltage Area Power Simple 1 1 5V Parallel 3.4 0.36 2.9V Pipelined 1.3 2.9V 0.39 Pipelined- Parallel 2.0V 3.7 0.2 C) Pipelined architecture Critical path = max [Tadder, Tcomp] Vpipe = 2.9V to maintain speed Cpipe = 1.15 Cref due to the added register ƒpipe = ƒref Ppipe = (1.15 Cref) (0.58 Vref)2 ƒref 0.39 Pref • Lower area than parallel architecture • Also reduces logic depth • Therefore consumes less power caused by hazards and races

40. Low Power Design Issues • Dynamic supply voltage scaling • Multi-threshold voltage CMOS • Near threshold computing • Low swing interconnect • Adaptive body biasing • Architecture-based voltage scaling • Arithmetic transformations • Low leakage design techniques 

41. Arithmetic Transformations Intermediate transition probability bit range LSB - MSB  Uncorrelated transition probability ≈ 1/2 0.5 Sign extension operation – Transition probability determined by frequency at which signal changes from positive to negative (or visa versa) random Transition probability transition region sign-extension 5 Bit # • Operation reduction • Reduce arithmetic operations by algorithmic transformations • 2) Choice of number representation • Two’s complement representation can result in significant switching activity when the signals being processed switch frequently around zero • 1 to 0 change will result in all bits toggling • Replace two’s complement with sign-magnitude representation • One bit for sign and remaining bits for magnitude • Most useful where large busses are being driven • Two’s complement conversion cost in capacitance << reduced switched bus capacitance • Log representation • Differential coding • Gray coding Decision is based on signal statistics, added capacitive overhead, area penalty, delay, latency, etc.

42. Low Power Design Issues • Dynamic supply voltage scaling • Multi-threshold voltage CMOS • Near threshold computing • Low swing interconnect • Adaptive body biasing • Architecture-based voltage scaling • Arithmetic transformations • Low leakage design techniques 

43. Leakage Current - Techniques and Related Issues S = n VT ln 10 100 mv/decade • Reduce stand-by power while maintaining high speed • Each 100 mv decrease in VT produces a ~10x increase in leakage current • Becomes worse with scaling • Leakage current is particularly important in burst mode IC’s • System is idle (or asleep), no computation occurring • Cell phone, pager • Acceptable for high IL during active mode but not during stand-by (or idle) mode

44. Techniques to Manage Leakage Current • Stack effect • Reduces sub-VTIL by forcing series transistors to all be off • Reverse body biasing to increase VT • Dual VT technology • High VT to reduce leakage currents • Low VT to provide high speed in critical paths

45. Dual VT Design Techniques • Most straightforward approach • Critical  low VT • Non-critical  high VT • Reduces sub-VTIL in active and stand-by modes • Less effective if many critical paths • Primary disadvantage • An additional process mask step

46. Transistor Sizing of High-VT Transistor • If width is too large, wastes area and power • If width is too small, too slow • Preferable to combine separate sleep transistor into a single common sleep transistor • MTCMOS circuits require insertion of additional series high-VT devices to limit leakage currents in standby mode • Difficult to size properly • Degrades performance since in series with signal path

47. Conclusions • Low power is required for longer battery life and to satisfy power density constraints • Optimization of supply voltage and threshold voltage is crucial to achieve minimum power under a certain frequency constraint • Several techniques for low power design have been proposed • Dynamic supply voltage scaling (reduces dynamic power) • Multi-threshold CMOS (reduces leakage power) • Low swing interconnect (reduces dynamic power) • Adaptive body biasing (reduces leakage power) • Parallel architecture (reduces dynamic power) • Arithmetic transformations (reduces dynamic power) • Transistor sizing (reduces dynamic power)

48. VTCMOS Circuit Techniques Self-substrate bias (SSB) Chip Leakage Circuit Monitor (LCM) VDD on/off I2 W2 M1 IREF WLCM “L” ILEAK LCM W1 ILEAKCHIP Two circuit techniques are needed • Feedback control of substrate bias by SSB and LCM for VTH compensation • A combination of a switch transistor which connects the substrate to VDD/VSS in the active mode and a substrate bias control by SSB and LCM which reverse biases the substrate in the stand-by mode • LCM activates SSB when IleakLCM > Iref • SSB lowers VBB by pumping out current from the substrate • VTH increases and IleakLCM is reduced • When IleakLCM < Iref, LCM stops SSB • ISUB gradually increases due to impact ionization and junction leakage, increasing VBB • VTH gradually decreases and IleakLCM increases • When IleakLCM > Iref, LCM activates SSB • VTH can be set to a target value, minimizing process-induced threshold voltage fluctuations

49. VTCMOS Circuit Techniques Leakage current detection ratio WCHIP – effective total channel width corresponding to the total leakage current in a chip - Vb, gate potential of TMI I2 is chosen to place Tw2 and Tw1 into the subthreshold region • Only a function of transistor size ratio - Independent of VDD, T, and process variations

50. Transistor Sizing with Variable VDD PDYN = pt• CL • VDD2• fCLK • Increase the size of the transistors • Faster operation • Linear increase in power (dependence to CL) • Reduce the power supply voltage to equalize delay • Quadratic reduction in power (dependence to VDD) What is the optimum size for low power?