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PIPELINES Parallel Level 1

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  1. PIPELINES Parallel Level 1 • Pipelines are an architectural enchancement that improves the performance of a computer system without increasing the clock speed • Pipelines take advantage of inherent parallelism in instructions • All instructions go through the same set of phases in the process of begin executed: • INSTRUCTION FETCH • INSTRUCTION DECODE • OPERAND FETCH • EXECUTION • RESULT STORE (not all architectures) Kennesaw State University

  2. PARALLEL STAGES • Do each stage in parallel, with different instructions in each stage • Instructions flow from one stage to the next Stages time IF DE OF EX RS DONE 1 1 2 2 1 3 3 2 1 4 4 3 2 1 5 5 4 3 2 1 6 6 5 4 3 2 1 7 7 6 5 4 3 2 etc. Load Time One Inst per cycle after first Kennesaw State University

  3. PIPELINE PERFORMANCE • k: stages in pipeline • t: time to do each stage (actually slowest stage) • n: number of instructions to be processed Time required for non-pipelined processor: = nkt Time required for pipelined processor: 1st instruction: kt (pipeline load) All after 1st (n-1 after 1st): (n-1)t = kt + (n-1)t Kennesaw State University

  4. PIPELINE SPEEDUP SPEEDUP is measured as SERIAL TIME divided by PARALLEL TIME Kennesaw State University

  5. PIPELINE EFFICIENCY • EFFICIENCY is measured as the ratio of SPEEDUP over NUMBER OR PROCESSING ELEMENTS (in this case stages) Ex: 100 instructions, 4 stages, Kennesaw State University