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# Digital Logic Design - PowerPoint PPT Presentation

Digital Logic Design. Lecture # 7 University of Tehran. Outline. Verilog More on Minimization by KM Don’t Care Terms Hazard Quine-McCluskey Method for Minimization. Verilog.

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### Digital Logic Design

Lecture # 7

University of Tehran

• Verilog

• More on Minimization by KM

• Don’t Care Terms

• Hazard

• Quine-McCluskey Method for Minimization

• Continuing our discussion on Verilog, consider for instance a situation where we want to simulate a circuit such as the below shown. The code for this circuit would look like this: module function(a, b, c, d, w); input a, b, c, d; output f; wire w, y; and #( , ) u1(w, a, b); nand #( , ) u2(y, c, d); nor #( , ) u3(f, y, w); endmodule

• As you can see we can also include timing conditions for the gates as we did for transistors. The only difference is that we have at most 2 values showing the transition to 1 and transition to 0 delay times. There is no third value included because at gate level, transition to Z doesn’t have any meaning.

• We saw before how switching functions of up to 5 variables could be minimized using karnaugh maps. We will now show a 6 variables karnaugh map which is practically the largest karnaugh map we will ever use.

• Adjacency rules are maintained as they were before. We can consider these four 4 variables maps stacked onto each other to help us visualize the adjacency rules between them. For instance, the term representing the four shown minterms would be

• This will be the largest karnaugh map we will ever use. Using karnaugh maps for switching functions of a larger number of variables would be impractical.

• In some functions, not all combinations of the used number of variables can occur. For instance when the input of a circuit is in BCD form, we will only be receiving inputs of the binary numbers 0000 through 1001, in other words we don’t care what the outputs to these particular conditions are, because they will not be occurring in our problem. When using a karnaugh map for minimization, these terms need not be covered necessarily and are only considered to be 1 if they help us in covering a larger arena with certain maps.

• Note: Don’t care terms can not be used to distinguish between implicants and prime implicants.

• Note: Don’t care terms are not specified to be 0 or 1 until after a mapping has been done. It is also not necessary to consider the same don’t cares of a function that we have mapped as 1s in a SOP form, as 1s when mapping for a POS form. Consider for instance a case where we want to map the following karnaugh map for both SOP and POS form.

• Consider the following gate structure and its timing diagram (numbers on the gates show their delays):

• As we can see after a period of time and after changes have occurred, ‘y’ finally becomes 1. But for a small period of time, both of the gates have 0 on their outputs and thus cause ‘y’ to become 0 for 5ns.

• Let’s look at what has happened more carefully: When the input of the circuit changes from 111 to 101, there shouldn’t actually be any change in the circuit’s output theoretically but because the delay of one of the two paths which ‘b’ is passing through to reach the output is more than the other, an unwanted pulse known as a glitch (or a 1-hazard in this case) is occurring where the output drops to 0 for 5ns.

• We would have never observed such problems by only taking the switching algebra to mind, because this is a problem caused by the physics of our realization.

• What we want to know is how to identify and solve such problems before they occur, that is while they are still potential hazards.

• Consider for instance the karnaugh map of the last example that we have:

• To identify where potential hazards may occur from a KM, we must realize the fact that there can only be a hazard where an input is passed through to the output by more than one path. That is, on the KM, potential hazards only occur when we move from one 1 to another when they are not covered in one map. Whether or not this potential hazards turn into reality depends on the actual gate timings. To eliminate such potential hazards we must map those particular 1s thus using redundant map.

• Example: Potential hazards: 01010001 01110011

• In these cases, we can’t be sure that hazards occur, but because of the disjoint mapping, it is possible. To eliminate this chance, we can add the map and write

• Quote: 0-hazards can occur in the same shape as 1-hazards but in POS representation of the circuit.

• Another type of hazard, which occurs less often than the hazards mentioned so far (static hazards) is called a dynamic hazard. There are two kinds of dynamic hazards with two different waveforms which are :

• It can be proven that dynamic hazards are results of static hazards. For instance it is quite obvious that the second waveform can occur as a result of two static hazards that occur after each other.

• The reason dynamic hazards occur less often is that they often involve a change in 2 variables of the switching function in a very short period or at one instance.

• Up until now, all methods of minimization we have used were practical for a small number of variables. For example, the KM was practical for at most 6 variable functions. For functions of a larger number of variables, we need method that can be applied to computer based minimization. One method that we can use for this means is the Quine-McCluskey method that uses the following steps. For example:

• It is obvious that only minterms that differ in one variable’s value can be combined. Thus we list our minterms so that they are in groups with each group having the same number of 1s. So the first step is ordering the minterms according to their number of 1s (0-cube list) as shown below for this example (In such groups, only minterms residing in adjacent groups have the chance to be combined.):

• Compare minterms of a group with those of an adjacent one to form 1-cube list. When doing the combining, we put checkmark alongside the minterms in the 0-cube list that have been combined.

• We do the same combination procedure of comparing adjacent group minterms to form 2-cubes, 3-cubes and so on. While doing so, it can be seen that only minterms of adjacent groups have the chance of being combined which have an X in the same position.

• PIs are those terms left without checkmarks. After identifying our PIs, we list them against the minterms needed to be covered in the following manner:

• To find a minimal cover, we first need to find essential PIs. To do this we need to find columns that only have one checkmark in them, the according row will thus show the essential PI. After identifying essential PIs, that are necessarily part of the cover, we cover any remaining minterms using a minimal set of PIs. In this example: