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Alireza Haghdoost 1 Hossein Asadi 1 Amirali Baniasadi 2

System-Level Vulnerability Estimation for Data Caches. Alireza Haghdoost 1 Hossein Asadi 1 Amirali Baniasadi 2 1 Sharif University of Technology, Tehran, Iran 2 University of Victoria, Canada haghdoost@ce.sharif.edu asadi@sharif.edu amirali@ece.uvic.ca.

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Alireza Haghdoost 1 Hossein Asadi 1 Amirali Baniasadi 2

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  1. System-Level Vulnerability Estimation for Data Caches Alireza Haghdoost1Hossein Asadi1Amirali Baniasadi2 1Sharif University of Technology, Tehran, Iran 2University of Victoria, Canada haghdoost@ce.sharif.edu asadi@sharif.edu amirali@ece.uvic.ca

  2. This Work: Accurate Vulnerability Modeling for Cache Memory Goal: Improving accuracy of previously suggested vulnerability factor Motivation: Read frequency and components error masking (previously ignored, significantly affect the accuracy ) Our Solution: SVF : System-level vulnerability factor Key Result Vulnerability estimation accuracy in cache (40%) 0011 • 0010 & 0011 = 0010 • 1010 & 0011 = 0010 0010 0010 1010

  3. Why Reliability Analysis for Cache ? • Error rate is expected to increase in cache • 92% of system reboots are initiated by soft-error occurring in cache [Shazli08] • Soft-error sources: α particles and neutrons strike • Reliability aware design is necessary • Having cost-effective design • Accurate vulnerability analysis • Need early design phase vulnerability estimation

  4. Failure in Time Reliability is quantified by Failure in Time (FIT) FIT = Raw_FITratex (TVF x AVF) • Raw_FITrate= Raw failure rate of devices and circuits • TVF= Timing Vulnerability Factor • AVF= Architectural Vulnerability Factor • AVFBP = %0 • AVFPC = %100 • Other components, AVFcache= ? (Our focus)

  5. Life Time Analysis • Typical cache block access VulBlk = (t2-t1) AVFBlk= (t2-t1)/t3 AVFcache=  AVFblk_i/number_blks Fill Read Evict Vulnerable Time t2 t3 t1 Blk

  6. Life Time Analysis • Advantages: • Early design vulnerability estimation • Less detailed model and single pass simulation • Disadvantages: • Overestimates AVF • Up to 260% discrepancy with Fault injection [Wang07] • Overlooking read frequency & error masking 6

  7. Read Frequency VulBlk1= t4 - t1 VulBlk1= (t2-t1) + (t3-t2) + (t4-t3)= t4 - t1 AVFBlk1 = AVFBlk2 = (t4-t1)/t5 Fill Evict Read1 Read2 Read3 Read1 Fill Evict Vul. Vul. Vul. Vul. Blk1 Blk2 Time Time t2 t2 t3 t3 t4 t5 t1 t1 t5 t4

  8. Error Masking • Lifetime analysis: VulBlk= (t2-t1) • Accurate analysis: VulBlk = 0 P(Masking)=1 Blki 8

  9. Our Solution: SVF • SVF considers read frequency & error masking • SVF: Percentage of errors that occur in a component and propagate to system outputs • SVF uses the following: • P(masking) = IOM • P(propagation) = 1 – IOM

  10. SVF Analysis SVi= SVcache=  SVi SVFcache= SVcache/ (total_exec).(cache_sizebyte) Fill Read2 Evict Read1 Byte ith Time t3 t1 t0 t2 (t1-t0).(1-IOMcpu) + (t2-t1).(1-IOMcpu) + (t1-t0) .IOMcpu.(1-IOMCpu)

  11. Detailed SV Analysis • Erroneous data in cache result failure: • Written-back to main memory • Read by CPU • SV different cases: • Case 1 : Clean byte • Case 2 : Dirty byte without write • Case 3 : Dirty byte with write

  12. SV Scenario on Clean Byte • Case 1 : Clean byte Fill Read2 Read1 Evict Readn Time tn t1 t0 t2 . . . Byte ith tev SV(F:Rn)= tn.(1-IOMcpu) + SV(F:Rn-1).IOMcpu

  13. SV Different Scenarios • Case 2 : Dirty byte without write Fill Read2 Read1 Write-Back Readn tn t1 t0 t2 . . . Byte ith twrite-back SV(F:Rn)= twrite-back

  14. SV different scenarios • Case 3: Dirty block with write Fill Read2 Read1 Write-Back write1 writek twk tr1 t0 tr2 . . . Byte ith tw1 twrite-back SV(F:Rn)= SV(F:W1)+…+SV(Wk-1:Wk)+ (twrite-back-twk)

  15. Methodology • sim-alpha simulator • F.I running in functional simulation mode • SVF calculation running in detailed simulation mode • SPEC2000 benchmarks • Processor configuration

  16. IOMcpu Estimation • Fault injection on load instructions • F.I= Fault injection point • Observe propagation on store instructions • O.P= Observation point • IOM = #Correct /# Total F.I O.P

  17. IOMcpu Sensitivity: Number of Runs IOM

  18. Vulnerability Factors for Write-back Data Cache VF

  19. Vulnerability Factors for Write-Through Data Cache VF

  20. SVFcache Accuracy Improvement vs AVF Accuracy

  21. Summary • System-level vulnerability modeling technique • Investigates read frequency & erorr masking • Our result • Large AVF-SVF discrepancy in storage components with long storing times. • WT cache • 40% improved accuracy 21

  22. Questions

  23. Backup Slide 1 • F.I Simulation Time for IOMcpu experiments

  24. Backup Slide 2 • Relax IOM probability for each read access to IOM for total reads • Reference model is AVF • Validation model based on Fault injection is under development • TVF cache is 50% • TVF = Timing Vulnerability Factor • TVFlatch= %50 • TVFSRAM=%100

  25. Backup slide 3 SVi= (t1-t0)(1-IOMcpu) +(t2-t1)(1-IOMcpu) +(t3-t2)(1-IOMcpu) + (t1-t0)IOMcpu(1-IOMcpu)+(t2-t1)IOMcpu(1-IOMcpu) + (t1-t0)IOM2cpu(1-IOMcpu) SVcache=  SVi SVFcache= SVcache/(TT×M) Fill Read2 Read3 Evict Read1 Time t1 t2 t3 t4 t0

  26. Backup Slide 4 • SVF for Instruction Scheduler ? SVFIS = IOMIU (1-IOMIU) CVFIS x ?

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