System Level Signal Integrity

1. System Level Signal Integrity Jeff Cain HW Engineering Manager

2. Outline • SI Engineering • Gigabit/second technology • Digital communication • Future

3. SI Engineering • Signal Integrity Engineer • This phrase/title did not exist 7 years ago • Technology was leading to a divide • No longer good enough to ‘hook it up to the logic analyzer’ • What does the waveform look like?

4. SI Engineering • Signal Integrity Engineer • Integral part of CAD layout • Design constraints for timing and SI • Setup & Hold violations

5. Packaging • All layers of packaging are examined • Layer 1 - Silicon • Layer 2 - Package • Layer 3 - Board • Layer 4 - Backplane • Layer 5 - Chassis to chassis

6. Busses & Clocks • TTL, GTL, LVTTL, PCI • SSTL • Source synchronous DDR to ~150MHz • Today • HSTL • Source synchronous DDR to ~500MHz • This summer • Matching and length rules for clocks

7. Tools • Simulation at system level is difficult • Gets complicated quickly • Too many aspect ratio problems • i.e. - A 5mil wide line that is 20inches long, with 15 bends • Tend to focus on small pieces

8. Power Rail Decoupling • Spray & Pray • Rules of thumb, past experience • Useable tools/methodologies are becoming available • Often proprietary

9. Measurement Techniques • TDR • Network Analyzer • Eye Diagrams

10. TDR/TDT • Well known technique • Differential • Excellent at finding impedance mismatches • Tektronix 11801

11. TDR Results

12. Network Analyzer • Method for characterizing frequency dependency • Now have the ability to drive differential or common or both • S21, S11 and group delay are most important parameters

13. Typical |S21|

14. Group Delay

15. SMA Daughter Card Connector & Via Backplane Connector & Via Daughter Card SMA dB dB/in dB dB/in dB dB/in dB SMA into Connector SMA into Connector dB/in dB dB/in dB dB/in Daughter Card Connector & Via Backplane Connector & Via Daughter Card VNA Model • Broke down each main area into a loss mechanism

16. Line Loss

17. Theory vs Measurement • Dielectric loss - found exactly for TEM • Skin effect loss approximation (1) D. M. Pozar, “Microwave Engineering”, John Wiley & Sons, 1998

18. Theory vs Measurement

19. Dielectric Loss vs Skin Effect

20. Conductor Loss vs Width

21. Connector Loss

22. Maximum Length Input = 1Vp-p Output = 0.3Vp-p

23. Eye Diagram • HP8133A • Generates pseudo random NRZ data • Use scope to measure eye diagram • Data shown is for 24” of FR4, 2 connectors, 6 vias and 2 SMAs

24. SerDes • Serializer/Deserializer • Input/Output is X bits at R bit rate • Output/Input is 1 bit at X*R bit rate • Available as discrete and integrated devices • 612Mb/s, 1.25Gb/s and 2.5Gb/s are common values

25. 1 Bit Time Peaking

26. 3.125 Gb/s Normal vs Peaked

27. Digital Communications • Problem is similar to digital communications problem • Satellites or cellular • BER is determined from energy/bit to noise power ratio W is signal bandwidth and R is bit rate

28. Digital Communication Transmitted pulse w/ pre-emphasis Received pulse Total at any given time t0 Total w/ crosstalk

29. Future Challenges for SI • Optics • Signal Integrity • Link Budgets • Optical Backplanes

30. Future Backplane Simulation

31. Future Backplane Simulation