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Pixel Frontend Electronics in 0.25  CMOS

Pixel Frontend Electronics in 0.25  CMOS. DMILL + Pixel design requirements  good match Considerable functionality inside of a pixel  design constrained by size (how much can you put in n x m  2 ) DMILL simply can not support the FE-D design in production

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Pixel Frontend Electronics in 0.25  CMOS

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  1. Pixel Frontend Electronicsin 0.25 CMOS • DMILL + Pixel design requirements  good match • Considerable functionality inside of a pixel •  design constrained by size (how much can you put in n x m2) • DMILL simply can not support the FE-D design in production • Radiation-tolerant CMOS design • CERN RD-49, FPIX for BTeV, ... • Pixel FE-I Roadmap • Technology/Design developments required • Test chips • Design reviews • Planning and status

  2. Plan as Presented in Pixel Baseline Review (11 ‘00) DONE DONE DONE DONE DONE

  3. Roadmap • Develop in two technologies • Baseline: order via CERN frame contract, Backup: TSMC • Insert test chip runs to cross-check (before full wafer run) • Minimize layout time (Small feature size  extra space. Use synthesis • + automated place-and-route wherever possible) • Maximize verification time (2 000 000 transistor, mixed-mode chip) • Submit 1st full-wafer run by end July ‘01 FE-I Design team Mario Ackers - Bonn Laurent Blanquart - Marseille now LBL (from 28 Feb. 01) Giacomo Comes - Bonn Peter Denes - LBL Kevin Einsweiler - LBL Peter Fischer - Bonn Ivan Perič - Bonn Emanuele Mandelli - LBL Roberto Marchesini - LBL (until 16 Jan 01) Gerrit Meddeler - LBL

  4. Technology / Design Developments Mixed-mode standard cell library (Modification of CERN / RAL library - Bonn) Implement Silicon Ensemble (to be able to autoroute standard cells - LBL) example - Pixel Logic

  5. Comparative Size Two pixels (analog) in DMILL Two pixels in 0.25 50 50

  6. In a Pixel Discr. Pixel Control and Calibration (charge injection) Trim DACs (Thresh) (Shaping) Preamp

  7. Digital Test Chip TSMC 0.25 Submitted 08 Jan ‘01 Structures to test SEU sensitivity of storage registers Pixel RAM block Irradiate Apr ‘01 OVP Std.+SEU tol(1) Shift Register Gate Rupture Diode Leakage Triple Majority Shift Register LVDS Rx DAC SEU tol(2) Register RAM Block

  8. Analog Test Chip • Submitted (CERN) 28 Feb 01 • Submitted (TSMC) 6 Mar 01 • Array of pixels along with • other analog functions • Preamp and discriminator • Trim DACs • Main DACs • 50 output buffer • Input capacitance test structure LVDS Rx+Tx Cap Array Pixel Matrix Cap Load

  9. Pixel Analog Pixel Digital CTRL RO Bias CTRL CEU Status - Ready to Assemble Final Chip Pixel Column Pair Schematic or HDL Layout In test chips EOC D: A: FE-D

  10. Planning (1) - Design/Fabricate FE-I Design and Layout Some design later than foreseen Some layout earlier than foreseen On schedule to submit by end-July

  11. Planning (2) - Characterization

  12. US ATLAS E.T.C.

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