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Control Structures in ARM

Control Structures in ARM. Implementation of Decisions Similar to accumulator instructions One instruction sets the flags, followed by another instruction that uses the flags to make the actual branch decision ARM compare and test instructions. Condition Codes.

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Control Structures in ARM

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  1. Control Structures in ARM Implementation of Decisions • Similar to accumulator instructions • One instruction sets the flags, followed by another instruction that uses the flags to make the actual branch decision • ARM compare and test instructions

  2. Condition Codes Conditional branch instructions make a decision to branch based on the state of the appropriate flag.

  3. ARM Branch Instructions Unconditional branch B (or BAL) branch always testing individual condition codes: bmi – branch on negative (N==1) bpl – branch on positive or zero (N==0) bvs– branch on overflow set (V==1) bvc – branch on overflow clear (V==0) bcs – branch on carry set (C==1) bcc – branch on carry clear (C==0)

  4. ARM Branch Instructions testing result of compare or other operation (signed arithmetic): beq–branch on equal (Z==1) bne–branch on not equal (Z==0) bls–branch on less than ((N xor V)==1) ble–branch on less than or equal ((Z or (N xor V))==1) bge–branch on greater than or equal ((N xor V)==0) bgt–branch on greater than ((Z or (N xor V))==0)

  5. Comparison Instructions • CMP – Compare: subtracts a register or an immediate value from a register value and updates condition codes • Examples: • CMP r3, #0 @ set Z flag if r3 == 0 • CMP r3, r4 @ set Z flag if r3 == r4 All flags are set as a result of this operation, not just Z.

  6. (true) a == 0 a == 0? (false) b = 1 Exit C if statement in ARM int a; int b; if(a == 0) b = 1; /* assume a is in r0, b is in r1 */

  7. (true) (a+b)>c a+b > c? (false) a += b Exit C if statement in ARM if((a+b)>c) a+=b; • ARM code: /* assume value of a is in r0, value of b is in r1, and value of c is in r2 */ add r3, r0, r1 cmp r3, r2 ble false @ branch to false when((a+b)>c) @ is false add r0, r0, r1 @ a = a+b /* now store content of r0 to [a] */false:

  8. (false) i != j (true) i == j i == j? f=g+h f=g-h Exit C if-else statement in ARM if(i == j) f=g+h; else f=g-h; ARM code: /* assume f is in r0, i is in r1, j is in r2, g is in r3, h is in r4, */ cmpr1, r2 @ Z = 1 if i==j beq true @ branch to true when i==j sub r0, r3, r4 @ f = g-h (false) b done @ branch to done true: add r0, r3,r4 @ f = g+h (true) done:

  9. Conditional execution in ARM An unusual ARM feature is that all instructions may be conditional: CMP r0, #5 @ if (r0 != 5) { ADDNE r1, r1, r0 @ r1 := r1 + r0 - r2 SUBNE r1, r1, r2 } • this removes the need for some short branches, improving performance and code density

  10. ARM Control Structures Implementing Loops • All for loops, while loops, and do-while loops have an implicit branch from the bottom to the top of the loop. • This branch instruction becomes explicit when stanslated into assembly. while loop @ assume a is in r0, b is in r1 while ( a <= 10 ) test: { cmpr0, #10 @ test condition a = a + b; bgtdone } add r0, r0, r1 b test done:

  11. Loops in C/Assembly for loop @ a: r0, b: r1, c: r2 for ( a = 1; a <= b; a++ ) mov r0, #1 { test: c *= a; cmp r0, r1 @ test condition } bgt done mul r2, r2, r0 rewritten as while loop add r0, r0, #1 a = 1; b test while ( a <= b ) done: { c *= a; a++; }

  12. Control Structures in ARM for loop, counted up from 0 to n-1 @ i: r0, n: r1 for ( i = 0; i < n; i++ ) { clrr0 <body> test: } cmpr0, r1 bgedone rewritten as while loop <body> i = 0; add r0, r0, #1 while ( i < n ) b test { done: <body> i++; } for loop, counted up from 1 to n for ( i = 1; i <= n; i++ ) { mov 1, %i_r <body> test: } cmp %i_r, n bg done nop rewritten as while loop <body> i = 1; while ( i <= n ) { inc %i_r <body> ba test i++; nop } done: for loop, counted down from to n to 1 for ( i = n; i > 0; i-- ) { mov n, %i_r <body> test: } cmp %i_r, 0 ble done nop rewritten as while loop <body> i = n; while ( i > 0 ) { dec %i_r <body> ba test i--; nop } done:

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