micro controller hardware architechture n.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
Micro controller hardware architechture PowerPoint Presentation
Download Presentation
Micro controller hardware architechture

Loading in 2 Seconds...

play fullscreen
1 / 11

Micro controller hardware architechture - PowerPoint PPT Presentation


  • 113 Views
  • Uploaded on

Micro controller hardware architechture. Scope. Hardware Diagram Operating Mode Architecture installing clock external memory attachment. Pin configuration. MCS51Core CPU Atmel 89S8252. Pins. Address/Port: High address/P2: 8 pins A8-A15 or Port 2

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'Micro controller hardware architechture' - jace


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
micro controller hardware architechture

Micro controller hardware architechture

CIT 673 Created by Suriyong

scope
Scope
  • Hardware Diagram
  • Operating Mode
  • Architecture
  • installing clock
  • external memory attachment

CIT 673 Created by Suriyong

pin configuration
Pin configuration

MCS51Core CPU

Atmel 89S8252

CIT 673 Created by Suriyong

slide4
Pins
  • Address/Port: High address/P2: 8 pins
    • A8-A15 or Port 2
  • Address/Data/Port: Low address/Data/P0
    • 8 pins
    • A0-A7/D0-D7/Port 0
  • Port: port 1 8 bits
  • Signal pin
    • ALE: Address Latch Enable :
      • active high, signal to express that the signal is low address at P0
    • PSEN: Program Strobe Enable:
      • active low, signal when access to external program memory
    • EA: External Access:
      • active low, signal to control the CPU to access the external memory
    • RST: CPU Reset input
  • Signal/Alternate function port pin : port 3
    • WR: Write signal to external data
    • RD: Read signal to external data
    • TXD: Transmit Data, serial communication
    • RXD: Receive Data, serial communication
    • External interrupt source and signal
  • Clock : pin X1 and X2
  • Power Supply : VCC:GND

CIT 673 Created by Suriyong

operating mode
Operating Mode
  • 1 chip mode
    • operating use only CPU and its SFR
  • Multi-chip mode
    • when extend or need more peripherals
    • such as extend external RAM, more I/O

CIT 673 Created by Suriyong

architecture
Architecture
  • busses
    • address bus
    • data bus
  • ports
  • registers
    • register that control CPU operating
  • clock signals
    • hardware connection
  • Address space
  • memory address decoding
  • External Input/output
    • address decoding and interfacing
  • Interrupt Hardware architechture

CIT 673 Created by Suriyong

slide8
BUS
  • Address BUS
    • 16 bit able to decode of 65536 address
    • Use alternate function of P2 as high address bus
    • P0 as low address bus and multiplex with data bus
    • use Address Latch Enable (ALE) signal as multiplex signal
    • need Latching IC : 74LS373 to latch the low address
  • Data bus
    • 8 bit
    • alternate function of P0
    • multiplex with low address bus
    • first as address, next as data

CIT 673 Created by Suriyong

external data and program memory accessing
External data and program memory accessing
  • when external memory is needed use Program Strobe ENable (PSEN) to signal to decode the memory
  • when PSEN
    • low: program memory is accessed and data is get after Read (RD) signal is active
    • high: data memory is accessed and data is get or write after RD or WR signal

CIT 673 Created by Suriyong

external memory diagram
External memory diagram

CIT 673 Created by Suriyong

cpu register
CPU Register
  • Unable to manipulate directly
  • PC: Program Counter
    • Contain the address of the code
  • ALU: Arithmetic Logical Unit
    • the calculation zone

CIT 673 Created by Suriyong