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"There Is More Than Moore in Automotive …". Hartmut Hiller Infineon Technologies AG Senior Director Design Methodology Business Group Automotive, Industrial & Multimarket. Body & Convenience Xenon Light, Seat Position, Climate Control, Dashboard. Powertrain

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there is more than moore in automotive

"There Is More Than Moore in Automotive …"

Hartmut Hiller

Infineon Technologies AG

Senior Director Design Methodology

Business Group Automotive, Industrial & Multimarket

some semi conductor enabled functions of a typical car
Body & Convenience

Xenon Light, Seat Position,Climate Control, Dashboard

Powertrain

Engine ControlTransmission ControlBattery Management

Climate Control

Airbag

Night Vision

Park DistanceControl

Steering

Transmission

Hybrid

Dashboard

Blindspot Detection

Engine

Suspension

CoolingFAN

TPMS

Mirror

Brake

BatteryManagement

Door

Light

ABS

Central Lock

ESP

AdaptiveCruise Control

Chassis

Active Suspension, Power Steering

Safety

Airbag, ABS Brakes,Adaptive Cruise Control

Some Semi-conductor enabled functions of a typical car

Nico Kelling (IFJ AIM MC)

automotive microelectronics trends more than 50 of value of electronics is semiconductors
Growth in % (1995 = 100%)

450%

CAGR

11.3%

Semiconductor

content of car

425%

Value of

Semiconductor per car

2008: 320 US$

2020: 700 US$

400%

350%

300%

Electronics

content of car

255%

CAGR

6.9%

250%

200%

Car volume

144%

150%

CAGR

2.6%

100%

1995

1997

1999

2001

2003

2005

2007

2009

Source: ZVEI

Automotive Microelectronics Trends  More Than 50% of $-value of Electronics is Semiconductors
full spectrum of semi conductor technologies is needed
Full spectrum of semi-conductor technologies is needed

Computing

Power Semicon.

High current

High voltage

High temperatures

Silicon Sensors

Special processes

High precision

Great robustness

Sensing

Actuating

Microcontrollers

50 m transistors

Non-volatile memory

SmartSensors

Smart Power

slide6
1000

130nm

90nm

Emerging Memories

100

2-year Cycle

Technology Node – Minimum structure (nm)

65nm

Bipolar CMOS DMOS

3-year Cycle

eFlash Automotive MC

22nm

DRAM ½ Pitch

MPU/ASIC ½ Pitch

10

1995

1998

2001

2004

2007

2010

2013

2016

Year of Production

While technologies for Automotive follow at a distance

Moore’s Law: Driver for CMOS & DRAM

Source: ITRS Roadmap, Infineon, Internet Announcements

the special challenges for automotive technologies
The special challenges for Automotive Technologies

1. Extended Temperature Range: -50° C to 175+° C

2. Extreme mechanical stress (vibration, pressure, temp. cycles)

3. Extreme voltages/currents for Power-Semiconductors (Switches)

4. Long term reliability requirement

5. Large eFlash with 10 years data stability

6. Demanding ESD / EMC / EOS requirements

7. Zero Defect Requirement

the special challenges for automotive technologies8
The special challenges for Automotive Technologies

QUALITY( No compromises )

This builds the basis for our RELIGION which is called

infineon s automotive excellence program
Infineon’s Automotive Excellence Program

44th Design Automation Conference

San Diego, June 2007

we deliver world class quality from day zero
Secure Ramp

Former

We deliver "World Class Quality" from Day Zero

Quality *

Effort

Wspw

Time

* := Functionality, Zero Defect, Yield, Reliability, Robustness, Spec. Corners

unfortunately world class does not come for free
Learning

Learning

Test-Chip

Learning

Product A-Step

Product A-Step

Product B-Step

Unfortunately "World Class" does not come for free

The Goal

Quality

Wspw

Test-Chip

Effort

Time

our today s top 3 challenges w o good eda solutions
Our today’s "Top 3 Challenges" (w/o good EDA solutions)

Today’s EDA Tools provide "sub-optimal" Support for:

1. The embedded Flash Challenge

2. EMC Modelling

3. To overcome the "Analogue / Digital Wall"

1 the embedded flash challenge
A typical InfineonHigh-End µC1. The embedded Flash challenge

The eFlash challenges:

1. Tremendous analogue complexity pushing the tool limits ( 18 Mio Transistors  100 Mio extr. Devices)

2. Complex Mixed Signal function; FSI with own CPU for calibration

3. Electro-Migration verification

4. Dynamic IR Drop verification

5. Hierarchical Extraction

6. True Latchup Issues (due to high Voltages during write/erase)

2 emc modelling
Chip

Real Layout

Abstraction via Own Tool

Netlist

Package

  • Simulations:
  • VDD/VSS-Currents
  • Voltage Drop
  • Noise Crosstalk
  • EME
  • ESD
  • Parasitic Resonances

EME Simulation Results

2. EMC Modelling
3 the digital analogue wall
Timing closure;

Behavioral Correctness;

non distrubant analogue

Transitor level opt.;

Transient behavior;

Noise; …

Sys- Level

Dig. Design

AMS Design

SIP

Abstraction

Abstraction

Abstraction

Abstraction

3. The digital / analogue Wall

Abstraction

1-2 Iterations / macro

Macro

+ FRUSTRATION 

AMS community / db

Full-Chip community / db

And that‘s what we strive for

Common database

& Common Methods (example: Full Chip Crosstalk analysis )

slide16
The "Monsters ahead":

Tomorrows "Top 3 Challenges"

1. Modelling Parasitic devices

2. "Adding Brain to Power"

3. On the Way to "Zero Pin Sensors"

1 modelling parasitic devices
 if potential drops below Vdd (!!! critical with inductive loads !!!)

"One" Problem:

Parasitic NPN

1. Modelling Parasitic Devices

Modelling of parasitic devices/substrates is "the blind spot" in today’s EDA (Example: ReverseCurrent Injection for Power-Semi):

Today’s solutions: Expert Reviews & Checklists to ensure that proper design measures are taken

But unfortunately you see such a problem the first time on Si(  lack of EDA supported methods )

2 adding brain to power
µ-Controller

Power-Chip

2. "Adding Brain To Power"

Next Step:

Current Product (MCM):

horizontal integration(based on IFX 130nm node)

and the Next Challenges (w/o good EDA answers):

1. Voltage Dependent Design Rules

2. New effects (parasitcs) due to substrate coupling  substrate Modelling

3. Diverging Time Constants (kHz  100s of MHz)

4. Diverging Current Ranges (µA  some A)

5. Thermal simulation with analogue view ( matching  isotherm req.)

6. Digital / Analogue / High Voltage Co-Design

7. . . . . . .

3 on the way to zero pin sensors
The Next Level of Sensor Integration(!!! truly autonomous !!!):3. On the Way to "Zero Pin Sensors"

European Commission #026461 – e-CUBES

and the Next (EDA) Challenges coming with it:

1. How to test an pin-less device (new BIST methods)?

2. Overall System Level verification  Full Range: mechanical thru High Speed-RF

3. Highly sophisticated System In Package (SIP) flow / methodology needed

4. Sophisticated Power Saving techniques

5. High density interchip wiring & interchip vias

6. Interchip Crosstalk

7. . . . . . .

conclusions
Conclusions

Quality & Reliability are the driving forces for Automotive

Products are facing (simultaneously) a broad range of challenges:

* Mechanical

* Thermal

* Robustness

* Mixed Signal Complexity

* ESD / EOS / EMC

The EDA issues shown are our prominent ones

beside

HW / SW integration, Funct. (MS) Verification, ESD robustness,. . . . . .

http www infineon com
http://www.infineon.com

Thank you for your attention

Hope you got some MORE insight

why

"There is MORE than MOORE in Automotive …"

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