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LOW VOLTAGE INHIBIT MODULE (LVI). Module Objective. By the end of this module you should be able to: Understand LVI system Understand LVI control Module exercise: Initialize the LVI module for Forced Reset when power drops below the trip point. IRQ. LVI. Direct Memory Access

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Presentation Transcript
slide3

Module Objective

  • By the end of this module you should be able to:
    • Understand LVI system
    • Understand LVI control
  • Module exercise:
  • Initialize the LVI module for Forced Reset when power drops below the trip point.
low voltage inhibit lvi module

IRQ

LVI

Direct

Memory

Access

Module

(DMA)

System

Integration

Module

(SIM)

Clock

Generation

Module

(CGM)

Timer

Interface

Module

(TIM)

68HC08

CPU

RESET

COP

BREAK

Internal Bus (IBUS)

Random

Access

Memory

(RAM)

Serial

Peripheral

Interface

(SPI)

Electronically

Programmable

ROM

Monitor

ROM

Serial

Communications

Interface

(SCI)

LOW VOLTAGE INHIBIT (LVI)MODULE
  • Monitors the VDD voltage
    • Programmable LVI reset
    • Programmable power consumption
    • Write-protected status and control register
lvi block diagram
LVI Block Diagram

V

DD

ST

OP

INSTRUCTION

(FROM MOR)

L

VISTOP

L

VIPWR

(FROM MOR)

(FROM MOR)

L

VIRST

V

> L

VI

= 0

LVI RESET

LOW VDD

DD

TRIP

DETECTOR

V

<

LV

I

= 1

DD

TRIP

L

VIOUT

lvi control

READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD

MOR

WRITE:

RESET: UNAFFECTED BY RESET

LVI CONTROL
  • LVI Enable in Stop Mode (LVISTOP)
    • If LVIPWR bit is at logic one, LVISTOP enables the LVI modules to operate during stop mode
      • 1 = LVI not disabled by STOP instruction
      • 0 = LVI disabled by STOP instruction
  • LVI Reset (LVIRST)
    • Enables reset when LVIOUT is set
    • MPU remains in reset until VDD rises above LVITRIP
    • Allow LVISETTLE time before enabling

1 = LVI reset enabled

0 = LVI reset disabled

  • LVI Power Enable (LVIPWR)
    • Applies power to the LVI analog circuitry
    • Disabling will stop current drain form the LVI
    • 1 = Power applied
    • 0 = Power not applied
lvi status flag

0 0 0 0 0 0 0

READ: LVIOUT

LVISR

WRITE:

RESET: 0 0 0 0 0 0 0 0

LVI Status Flag
  • LVI Status Register (LVISR)
    • Used to monitor the state of VDD
    • Flags VDD voltages below LVI TRIPF
      • LVIOUT Bit Indication
        • VDD LVIOUT
        • VDD > LVI TRIPF 0
        • VDD < LVI TRIPF 1
        • LVI TRIPF < VDD< LVI TRIPR Previous Value
    • Allow LVISETTLE time before polling
additional information low power modes
Additional Information- Low Power Modes -
  • Low Power modes
    • STOP
      • When LVIPWR = 1, the LVI is active after a Stop
    • WAIT
      • When LVIPWR = 1, the LVI is active after a Wait
      • A LVI Reset will bring the MCU out of Wait mode
register summary

READ: 0 LVISTOP LVIRST LVIPWR SSREC SEC STOP COPD

MOR

WRITE:

RESET: UNAFFECTED BY RESET

0 0 0 0 0 0 0

READ: LVIOUT

LVISR

WRITE:

RESET: 0 0 0 0 0 0 0 0

Register Summary