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### Chapter 15Multistage Amplifiers

Microelectronic Circuit Design

Richard C. Jaeger

Travis N. Blalock

Microelectronic Circuit Design

McGraw-Hill

Chap 15 - 1

Chapter Goals

- Understand analysis and design of ac-coupled multistage amplifiers including voltage gain, input and output resistances and small signal limitations.
- Understand analysis and design of dc-coupled multistage amplifiers.
- Discuss characteristics of Darlington configuration and cascode amplifier.
- Explore dc and ac properties of differential amplifiers.
- Understand basic three-stage op amp.
- Explore design of class-A, class-B, class-AB output stages.
- Discuss characteristics and design of electronic current sources.
- Continue understanding the use of SPICE in circuit analysis.

Microelectronic Circuit Design

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Chap 15 - 2

AC-coupled Amplifiers: Description

- MOSFET M1operating in C-S configuration provides high input resistance and moderate voltage gain.
- BJT Q2 in C-E configuration, the second stage, provides high gain.
- BJT Q3, an emitter-follower gives low output resistance and buffers the high gain stage from the relatively low load resistance.
- Bias resistors are replaced by
- Input and output of overall amplifier is ac-coupled through capacitors C1 and C6.
- Bypass capacitors C2 and C4 are used to get maximum voltage gain from the two inverting amplifiers.
- Interstage coupling capacitors C3 and C5 transfer ac signals between amplifiers but provide isolation at dc, and prevent Q-points of the transistors from being affected.

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Chap 15 - 4

AC-coupled Amplifiers: Equivalent Circuits

AC Equivalent

Small-signal Equivalent

DC Equivalent

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Chap 15 - 5

AC-coupled Amplifiers: Input Resistance and Voltage Gain

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Chap 15 - 6

AC-coupled Amplifiers: Output Resistance

To find output resistance, test voltage is applied at amplifier output.

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Chap 15 - 7

AC-coupled Amplifiers: Current and Power Gain

Input current delivered to amplifier from source is

and current delivered to load by amplifier is

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Chap 15 - 8

AC-coupled Amplifiers: Input Signal Range

- For first stage,
- For second stage,
- For third stage,
- On the whole,

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Chap 15 - 9

AC-coupled Amplifiers: Methods to Improve Voltage Gain

- Gain of C-S amplifier is inversely proportional to square root of drain current, so voltage gain could be increased by reducing ID1 while maintaining a constant voltage drop across RD1. Signal range could be improved by increasing current in output stage and voltage drop across RE3.
- Q1 could be replaced with a FET. This could cause gain loss in third stage since gain of C-D amplifier is typically < that of a C-C stage. However, this loss could be made up by improving gain of first and second stages.

Microelectronic Circuit Design

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Chap 15 - 10

Common-Emitter Cascade

If gain is limited by interstage resistances, each stage has a gain of about -10VCC and overall gain is:

If gain is limited by input resistance of transistors, it is given by:

Normally as signal and power levels usually increase in each successive stage of most amplifiers. Since bo< 10VCC , this case often represents the actual limit.

To achieve maximum gain, several C-E stages can be cascaded.

For the final stage,

For all other stages,

Microelectronic Circuit Design

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Chap 15 - 11

Direct-coupled Amplifiers: Circuit

- Bypass capacitors- C2 and C4 affect gain at low frequencies but don’t inherently prevent the amplifier from operating at dc.
- Symmetrical power supplies are used to set Q-point voltages at input and output to about zero.
- Alternating pnp or p-channel and npn or n-channel transistors are used from stage to stage to take maximum advantage of available power supply voltage.

- Coupling capacitors in series with signal path- C1, C3, C5, and C6 are eliminated as they prevent the amplifier from providing gain at dc or very low frequencies.
- Additional bias resistors in individual stages are also removed, making design less expensive.

Microelectronic Circuit Design

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Chap 15 - 12

Direct-coupled Amplifiers: DC Analysis

So, ID = 6.66. mA (which would produce 10.7 V drop across RS1 and cut off FET) or ID =5.29 mA (correct value).

IB2 << ID,

which is enough to pinch off M1.

bF2 =150, so IC2 =1.83 mA and IB2 = 12.2 mA.

IB3 << IC2,

which < 0.7 V , so Q2 is in active region.

Voltage at drain of M1 provides base bias for Q2 and voltage at collector of Q2 provides base bias for Q3. All transistors operate in active region irrespective of direct connection between stages.

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Chap 15 - 13

Direct-coupled Amplifiers: DC Analysis (contd.)

bF3 = 80, so IC3 =3.94 mA and IB3 = 49.3 mA

thus Q3 is in active region.

There is an offset voltage of 0.4 V at output and a nonzero dc current exists in 250 W load resistor. In an ideal design, offset voltage would be zero and no dc current would appear in load.

Based on Q-point values, small-signal parameters can be calculated.

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Chap 15 - 14

Direct-coupled Amplifiers: AC Analysis

- Dc coupling requires fewer components than ac-coupling but Q-points of various stages become interdependent.
- If Q-point of one stage shifts, Q-points of all other stages might also shift.

- Values of interstage capacitors are higher than those in ac-coupled amplifier due to absence of bias resistors.
- Overall characteristics are similar to those in ac-coupled amplifier as Q-points and small-signal parameters of transistors are similar

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Chap 15 - 15

Direct-coupled Amplifiers: Darlington Circuit

AC Analysis: For the composite transistor,

Darlington circuit behaves similar to the single transistor but has a current gain given by the product of current gains of individual transistors.

DC Analysis: For bF1, bF2 >>1,

VBE of composite transistor = 2 diode voltage drops. So VCE >(VBE1 + VBE2) .

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Chap 15 - 16

Direct-coupled Amplifiers: Cascode Circuit

AC Analysis: For the composite transistor,

Cascode circuit is cascade connection of C-E and C-B amplifiers, used in high gain amplifiers and high output resistance current sources.

DC Analysis: For a high current gain,

For forward-active operation of Q2,

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Chap 15 - 17

Differential Amplifiers

- Differential-mode output voltage is the voltage difference between collectors, drains of the two transistors.Ground referenced outputs can also be taken from collector/drain.
- Ideal differential amplifier uses perfectly matched transistors.

- Differential amplifiers,also considered the C-C/C-B cascade, eliminate the bypass capacitors as well as the external coupling capacitors at the input and output of direct-coupled amplifiers.
- Each circuit has two inputs.

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Chap 15 - 18

Bipolar Differential Amplifiers: DC Analysis

Terminal currents are also equal.

Both inputs are set to zero, emitters are connected together.

If transistors are matched,

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Chap 15 - 19

Small-Signal Transfer Characteristic

The current switch is a digital application of the differential amplifier. Large-signal transfer characteristic of differential amplifier is given by:

Even-order distortion terms are eliminated.This increases signal-handling capability of differential pair. For small-signal operation, liner term must be dominant. Hence, we set the third-order term to be one-tenth the linear term.

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Chap 15 - 20

Bipolar Differential Amplifiers: DC Analysis (Example)

- Problem:Find Q-points of transistors in the differential amplifier.
- Given data:VCC=VEE=15 V, REE=RC=75kW, bF =100
- Analysis:

Due to symmetry, both transistors are biased at Q-point (94.4 mA, 8.62V)

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Chap 15 - 21

Bipolar Differential Amplifiers: AC Analysis

Add = differential-mode gain

Acd = common-mode to differential-mode conversion gain

Acc = common-mode gain

Adc = differential mode to common-mode conversion gain

For ideal symmetrical amplifier, Acd = Adc = 0.

Purely differential-mode input gives purely differential-mode output and vice versa.

Circuit analysis is done by superposition of differential-mode and common-mode signal portions.

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Chap 15 - 22

Bipolar Differential Amplifiers: Differential-mode Gain and Input Resistance

Emitter node in differential amplifier represents virtual ground for differential-mode input signals.

Output signal voltages are:

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Chap 15 - 23

Bipolar Differential Amplifiers: Differential-mode Gain and Input Resistance (contd.)

Differential-mode gain for balanced output, is:

If either vc1 or vc2 is used alone as output, output is said to be single-ended.

Differential-mode input resistance is small-signal resistance presented to differential-mode input voltage between the two transistor bases.

If vid =0, . For single-ended outputs,

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Chap 15 - 24

Bipolar Differential Amplifiers: Common-mode Gain and Input Resistance

Both arms of differential amplifier are symmetrical. So terminal currents and collector voltages are equal. Characteristics of differential pair with common-mode input are similar to those of a C-E (or C-S) amplifier with large emitter (or source) resistor.

Output voltages are:

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Chap 15 - 25

Bipolar Differential Amplifiers: Common-mode Gain and Input Resistance (contd.)

Common-mode gain is given by:

For symmetrical power supplies, common-mode gain =0.5. Thus, common-mode output voltage and Acc is 0 if REE is infinite. This result is obtained since output resistances of transistors are neglected. A more accurate expression is:

Therefore, common-mode conversion gain is found to be 0.

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Chap 15 - 26

Common-Mode Rejection ratio (CMRR)

- Represents ability of amplifier to amplify desired differential-mode input signal and reject undesired common-mode input signal.
- For differential output, common-mode gain of balanced amplifier is zero, CMRR is infinite. For single-ended output,
- For infinite REE , CMRR is limited by bomf . If term containing REE is dominant

Thus for differential pair biased by resistor REE , CMRR is limited by available negative power supply.

- Due to mismatches, , gives fractional

mismatch between small-signal device parameters in the two arms of differential pair. Hence gmREE product is maximized.

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Chap 15 - 27

Analysis of Differential Amplifiers Using Half-Circuits

- Half-circuits are constructed by first drawing the differential amplifier in a fully symmetrical form- power supplies are split into two equal halves in parallel, emitter resistor is separated into two equal resistors in parallel.
- None of the currents or voltages in the circuit are changed.
- For differential mode signals, points on the line of symmetry are virtual grounds connected to ground for ac analysis
- For common-mode signals, points on line of symmetry are replaced by open circuits.

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Chap 15 - 28

Bipolar Differential-mode Half-circuits

Direct analysis of the half-circuits yield:

Applying rules for drawing half-circuits, the two power supply lines and emitter become ac grounds. The half-circuit represents a C-E amplifier stage.

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Chap 15 - 29

Bipolar Common-mode Half-circuits

- All points on line of symmetry become open circuits.
- DC circuit with VIC set to zero is used to find amplifier’s Q-point.
- Last circuit is used for for common-mode signal analysis and represents the C-E amplifier with emitter resistor 2REE.

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Chap 15 - 30

Bipolar Common-mode Input Voltage Range

For symmetrical power supplies, VEE >> VBE, and RC = REE,

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Chap 15 - 31

Biasing with Electronic Current Sources

- Differential amplifiers are biased using electronic current sources to stabilize the operating point and increase effective value of REE to improve CMRR
- Electronic current source has a Q-point current of ISS and an output resistance of RSS as shown.
- DC model of the electronic current source is a dc current source, ISS while ac model is a resistance RSS.

SPICE model includes both ac

and dc models.

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Chap 15 - 32

MOSFET Differential Amplifiers: DC Analysis

and

Op amps with MOSFET inputs have a high input resistance and much higher slew rate that those with bipolar input stages.

Using half-circuit analysis method, we see that IS = ISS /2.

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Chap 15 - 33

Small-Signal Transfer Characteristic

MOS differential amplifier gives improved linear input signal range and distortion characteristics over that of a single transistor.

Second-order distortion product is eliminated and distortion is greatly reduced. However some distortion prevails as MOSFETs are nor perfect square law devices and some distortion arises through voltage dependence of output impedances of the transistors.

For symmetrical differential amplifier with purely differential-mode input

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Chap 15 - 34

MOSFET Differential Amplifiers: DC Analysis (Example)

- Problem:Find Q-points of transistors in the differential amplifier.
- Given data:VDD=VSS=12 V, ISS =200 mA, RSS = 500 kW, RD = 62 kW,l = 0.0133 V-1, Kn = 5 mA/ V2, VTN =1V
- Analysis:

To maintain pinch-off operation of M1 for nonzero VIC ,

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Chap 15 - 35

MOSFET Differential Amplifiers: Differential-mode Input Signals

Source node in differential amplifier represents virtual ground

Differential-mode gain for balanced output is

Gain for single-ended output is

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Chap 15 - 36

MOSFET Differential Amplifiers: Common-mode Input Signals

Electronic current source is modeled by twice its small-signal output resistance representing output resistance of the current source.

Common-mode half-circuit is similar to inverting amplifier with 2RSS as source resistor.

Thus, common-mode conversion gain= 0

Due to infinite current gain of FET, ro can be neglected.

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Chap 15 - 37

Common-Mode Rejection ratio (CMRR)

- For purely common-mode input signal, output of balanced MOS amplifier is zero, CMRR is infinite. For single-ended output,
- RSS (which is much > REE and thus provides more Q-point stability) should be maximized.
- To compare MOS amplifier directly to BJT amplifier, assume that MOS amplifier is biased by
- From given data in example, MOS amplifier’s CMRR=54 or 35 dB (almost 10 dB worse than BJT amplifier).To increase CMRR in BJT and FET amplifiers, current sources with higher RSS or REE are used.

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Chap 15 - 38

Two-port model for Differential Amplifiers

Two-port model simplifies circuit analysis of differential amplifiers.

Expressions for FET are obtained by substituting RSS for REE.

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Chap 15 - 39

Differential Amplifier Design (Example)

- Problem:Find Q-points of transistors in the differential amplifier.
- Given data:Adm=40 dB, Rid >250 kW,single-ended CMRR> 80 dB, VICat least ±5V, MOSFETs with: l = 0.0133 V-1, Kn’ = 50 mA/ V2, VTN =1V,
- BJTs with : bF =100, VA =75V, IS =0.5 fA
- Assumptions: Active-region operation, symmetrical power supplies, bo = bF, vid maximum of ±30 mV.
- Analysis:
- Adm=40 dB =100. To achieve this gain with resistively loaded amplifier, we use BJT. For Adm = gm RC =40 IC RC , required gain can be obtained with voltage drop of 2.5 V across RC.
- For bipolar differential amplifier, Rid =2rp, so, rp =125 kW.

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Chap 15 - 40

Differential Amplifier Design (Example contd.)

Choose IC = 15 mA to provide safety margin. So RC =2.5 V/15 mA =167 kW.

Choose RC = 180 kW as the nearest value with 5% toleranceand alos to compensate for neglecting ro in the analysis.

VICof 5V requires collector voltage to be at least 5 V at all times. We also know that vid can be a maximum of ±30 mV for linearity. So ac component of differential output will not be greater than 100(0.03 V)=3V, half of which appears at each collector. Thus dc signal across RC won’t exceed 4 V( 2.5 V dc + 1.5 V ac) and positive power supply must fulfill

Choose VCC=10 V to dive desired margin of 1 V, For symmetrical supplies, VEE = -10 V. Single-ended CMRR of 80 dB needs

Choose current source with IEE

=30 mA and REE > 20 MW

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Chap 15 - 41

Two-stage Prototype of an Op Amp

- For higher gain, pnp C-E amplifier is connected at output of the input stage differential amplifier.
- Virtual ground at emitter node allows input stage to achieve full inverting amplifier gain without needing emitter bypass capacitor.
- Pnp transistor permits direct coupling between stages, allows emitter of pnp to be connected to ac ground and provides required voltage level shift to bring output back to zero.
- Bypass and coupling capacitors are thus eliminated.

Differential amplifier provides desired differential input,CMRR and ground referenced output as the input stage of op amp.

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Chap 15 - 42

Two-stage Op Amp: DC Analysis

This circuit requires a resistance in series with emitter of Q3 to stabilize Q-point (as collector current of Q3 is exponentially dependent on base-emitter voltage), at the expense of voltage gain loss.

From dc equivalent circuit, IE1= IE2 = I1 /2. If base current of Q3 is neglected and C-B current gains are one,

As both inputs are zero, output also=0

IS3 is saturation current. For zero offset voltage

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Chap 15 - 43

Two-stage Op Amp: AC Analysis (Differential Mode)

Half-circuit can be constructed from ac equivalent circuit in spite of asymmetricity, as voltage variations at collector of Q2 don’t substantially alter transistor current in forward-active operation region.

From small-signal circuit model,

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Chap 15 - 44

Two-stage Op Amp: AC Analysis (Differential Mode contd.)

This can be rewritten as

Base current of Q3 is neglected so, IC2RC=VBE3=0.7 V, IC3R=VEE,

Upper limit onIC2 and I1 is set by maximum dc bias

current at input, lower limit on IC3 is set by minimum

current to drive total load impedance at output.

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Chap 15 - 45

Two-stage Op Amp: AC Analysis (Common Mode)

From ac equivalent circuit for common-mode inputs,

For differential-mode inputs, collector current was

Thus,

From ac equivalent circuit, we observe that circuitry beyond collector of Q2 is same as that in differential mode half-circuit. The difference in collector currents causes difference in output voltage.

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Chap 15 - 46

Improving Op Amp Voltage Gain

Overall amplifier gain decreases rapidly as the quiescent current of second stage decreases. Voltage gain can improve if resistor in second stage is replaced by current source with R2 >> ro3, if R2 is neglected,

This expression can be reduced to

Output resistance is degraded, amplifier more represents transconductance amplifier than a true low output resistance voltage amplifier.

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Chap 15 - 47

Reducing Output Resistance

From ac equivalent circuit,

A C-C stage is added to the prototype to maintain voltage gain but reduce output resistance.

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Chap 15 - 48

Three-Stage Bipolar Op Amp Analysis

- Problem: Find differential-mode gain, CMRR, input and output resistances.
- Given data:VCC=VEE=15 V, bo1 = bo2 = bo3 = bo4 =100, VA3 =75V, I1 = 100 mA, I2 = 500 mA, I3 = 5 mA, R1 = 750 kW , RL = 2 kW, R2 and R3 are infinite.
- Analysis:

Voltage at node 3 is one base-emitter voltage drop above zero. VEC3=15-0.7=14.3 V.

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Chap 15 - 49

Three-Stage Bipolar Op Amp Analysis (contd.)

Overall gain is lower because of lower gain of first stage (since rp3 << RC) and lower gain than expected for second stage (as reflected loading of RL is of same order as ro3).

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Chap 15 - 50

CMOS Op Amp Prototype: Circuit

- Differential amplifier (M1 and M2) followed by C-S stage M3 and source follower M4.
- Current sources are used to bias differential input and source follower stages and as load for M3.

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Chap 15 - 51

CMOS Op Amp Prototype: AC Analysis

Design freedom is higher than in bipolar case due to Q-point dependence of mf. Operating currents should be reduced and M3 should have small l to achieve higher gain.Input bias current doesn’t restrict ID1 as IG =0.

Since source follower has unity gain,

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Chap 15 - 52

BiCMOS Amplifiers

- Second gain stage uses BJT with superior amplification factor than FET.
- RE increases voltage across RD2 and hence the voltage gain of first stage without reducing amplification factor of Q1.
- Follower stage uses another FET to maximize second-stage gain while maintaining reasonable output resistance.

- Integrated circuit processes that offer combination of bipolar and MOS transistors or bipolar transistors and JFETs are called BiCMOS and BiFET technologies respectively.
- Input PMOS transistors give high input resistance, can be biased at relatively high input currents, which can improve slew rate.

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Chap 15 - 53

Op Amp Output Stages

- Output stage is designed to provide low output resistance and relatively high current drive capability.
- Followers: Class-A amplifiers- transistors conduct during full 3600 of signal waveform, conduction angle =3600.
- Push-pull: Class-B- each of the two transistors conducts during 1800of signal wavefrom, conduction angle =1800.
- Class-AB: Characteristics of Class-A and Class-B are combined, most commonly used as output stage in op amps.

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Chap 15 - 54

Source-Follower: Class-A Output Stage

For a source-follower,difference between input and output voltages is fixed and voltage transfer characteristic is as shown. If load resistor is connected to output, total source current:

vMIN = -ISS RL and iS=0, M1cuts off when vI = -ISS RL + VTN.

If output signal is given by:

Efficiency of amplifier is given by:

Low efficiency is due to current ISS that constantly flows between the two supplies.

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Chap 15 - 55

Class-B Push-Pull Output Stage

Improve efficiency by operating transistors at zero Q-point current eliminating quiescent power dissipation. NMOS transistor is a source-follower for positive input signals and NMOS transistor is a source-follower for negative input signals.

Since neither transistor conducts when,

output waveform suffers from a dead-zone or crossover distortion.

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Chap 15 - 56

Class-AB Amplifiers

The required bias voltage can be developed as shown.We assume that bias voltage splits equally between gate-source(or base-drain) terminals.

Currents are given by

Benefits of Class-B amplifier can be maintained without dead zone by biasing transistors into conduction but at a low quiescent current level (<< peak ac current delivered to load). For each transistor, 1800< conduction angle <3600.

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Chap 15 - 57

Short-Circuit Protection

High current, high power dissipation or direct destruction of base-emitter junction can destroy the BJT if output of a follower circuit is accidentally shorted to ground. Q2 is added to protect the emitter follower.

Normally, voltage across R is <0.7 V, Q2 is cutoff. Q2 turns on to shunt extra current away from base of Q1. IE1 is

limited to

For complementary output stage, similar

current-limiting circuitry is used. In

MOSFET complementary output stages,

output current is limited to

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Chap 15 - 59

Transformer Coupling: Follower

Transformer provides impedance transformation by n2 . From ac equivalent circuit,transistor must drive

Transformer restricts operation to frequencies >dc.

Transformer coupling is used in amplifiers to achieve high voltage gain and efficiency while delivering power to low impedance loads.

Coupling capacitor blocks dc path through primary of transformer.

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Chap 15 - 60

Transformer Coupling: Inverting Amplifier and Class-B Output Stage

Inductance permits signal voltage to swing symmetrically above and below VDD.

As both quiescent operating currents = 0, emitters can be directly connected to transformer primary.

At dc, transformer is a short circuit, quiescent operating current is supplied through transformer primary. At signal frequency load n2RL is presented to transistor.

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Chap 15 - 61

Electronic Current Sources: Introduction

- Current through ideal current source is independent of voltage across its terminals and the output resistance is infinite.
- In electronic current sources, current depends on voltage across the terminals and they have a finite output resistance.

Current source

Current sink

Single-transistor current sources operate in only one quadrant of i-v space but realize very high output resistances.

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Chap 15 - 62

Current Sources: Figure of Merit

is used as a figure of merit for comparing different current sources.

For a given Q-point current, VCS represents the equivalent voltage that will be needed across a resistor to achieve same output resistance as given current source.

For resistor:

For BJT:

For MOSFET:

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Chap 15 - 63

Higher Output Resistance Sources

For MOSFET:

Output resistance of the current source can be increased by placing a resistor in series with the emitter or source of the transistor.

For BJT:

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Chap 15 - 64

Multiple Output Current Sources

Assume equal current gains for all BJTs.

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Chap 15 - 65

Multiple Output Current Sources (contd.)

Output resistances of the three current sources are given by:

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Chap 15 - 66

Bipolar Transistor Current Source Design Example

- Problem: Design a current source with the largest possible output voltage range that meets the given output resistance specification.
- Given data:VEE = 15 V, Io = 200 mA, IEE < 250 mA, Rout > 2 MW, BJTs available with (bo, VA) = (80, 100 V) and (150, 75 V), VB must be as low as possible.
- Assumptions: Active region and small-signal operating conditions. VBE = 0.7 V, VT = 0.025 V, choose Vo = 0 V as representative output value.

Analysis:

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Chap 15 - 67

Bipolar Transistor Current Source Design Example (contd.)

Both BJTs can satisfy these conditions. But, we choose BJT (150, 75V) with higher boVA product.

Total current < 250 mA. As output current is 200 mA, maximum of 50 mA can be used by base bias network. Current used by base bias network must be 5 to 10 times base current of BJT (1.33 mA for BJT with a current gain of 150). So bias network current =20 mA.

Large RBB reduces output resistance and output compliance range (increase VBB).Trading increased operating current for wider compliance range, choose bias network current of 40 mA.

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Chap 15 - 68

Bipolar Transistor Current Source Design Example (contd.)

- Following set of equations can be used in a spreadsheet analysis to determine design variables. Primary design variable is VBB which can be used to determine other variables.

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Chap 15 - 69

Bipolar Transistor Current Source Design Example (contd.)

- From spreadsheet, smallest VBB for which output resistance > 10MW with some safety margin is 4.5 V, resulting output resistance is 10.7MW.
- Analysis of circuit with 1% resistor values gives Io = 200 mA and supply current = 244 mA.
- Final current source design is as shown.
- MOSFET current source design can also be analyzed in similar manner.

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Chap 15 - 70

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