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Chapter5: Synchronous Sequential Logic – Part 1. Origionally By Reham S. Al- Majed. Outline. Introduction. Sequential Circuits Types of SC. Latches Flip flops SR FF. D FF. JK FF. T FF. Introduction. The circuits considered thus far have been combinational

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Chapter5: Synchronous Sequential Logic – Part 1


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    1. Chapter5: Synchronous Sequential Logic– Part 1 Origionally By Reham S. Al-Majed Imam Muhammad Bin Saud University

    2. Outline • Introduction. • Sequential Circuits • Types of SC. • Latches • Flip flops • SR FF. • D FF. • JK FF. • T FF.

    3. Introduction • The circuits considered thus far have been combinational • The output depends only on the current inputs. • Most systems in practice include storage elements. • Sequential logic.

    4. Sequential Circuits • It consists of: • Combinational circuit. • Storages element. • Storage elements are devices capable of storing binary information. • The binary information stored in these elements at any given time defines the state of the SC at that time.

    5. Sequential Circuits • The SC receives binary information from: • External input. • Present/Current state of storage element. • The next state in the storage element is a function of: • External input. • Present/Current state. • The SC is specified by a time sequence of inputs, outputs, and internal states. Next State Current State

    6. Sequential Circuits • Two main types of SC according to the timing of their signals: • Synchronous SC: • The activity within the circuit and the resulting updating of stored values is synchronized to the occurrence of clock pulses. • Asynchronous SC: • Depends upon the input signals at any instant of time and the order in which the inputs change. • Difficult to design.

    7. Synchronous Sequential Circuits • Synchronization is by timing device called clock generator  clock signal (denoted by clock or clk) periodic train of clock pulses. • Storage elements are affected only with the arrival of each pulse. • In clocked SC: • The clock signal determine whenchanges will occur. • The other signals (e.g. inputs ) determine what are the changes that affect storage elements.

    8. Clock Signal • A sequence of 1s and 0s (ON and OFF periods) Positive edge Transition (rising edge) Positive pulses/level 1 0 Negative edge Transition (falling edge) Negative pulses/level

    9. Storage Element • A storage element can maintain a binary state (0,1) indefinitely, until directed by an input signal to switch states. • The momentary change in the storage element state is called a trigger. • Two types of triggering: • Pulse-triggered (Level-Sensitive) • Edge-triggered • Positive edge-triggered (from 0 to 1) • Negative edge-triggered (from 1 to 0) • Main difference between storage elements: • Number of inputs they have. • How the inputs affect the binary state.

    10. Storage Element • Two main types of storage elements: • Latches • Operate with signal levels. • Called level-sensitive. • Not practical for use in synchronous sequential circuits • Flip-Flops • Controlled by clock transition. • Called edge-sensitive. • Flip-Flips are built with latches • Used in clocked SC.

    11. Latches • A latch is binary storage element • Can store a 0 or 1 • It is the most basic storage element. • It is easy to build. • The trigger of a latch start as soon as the clock pulse changes to the logic-1 level. • The new state of a latch appears at the output while the pulse is still active. • Latches respond to new input values as clock pulse is still at logic-1 level.

    12. Latch circuits are not suitable in synchronous logic circuits. • Any change in the excitation input immediately causes a change in the latch output. • This leads to the edge-triggered memory elements, called flip-flops. • Output transitions occur at a specific level of the clock pulse • Otherwise, the ff is unresponsive to further changes until the clock pulse returns to 0 and another pulse occurs

    13. Flip-Flop • A FF is a binary storage element that can store 0 or 1 • a FF maintains a binary state until directed by a clock pulse to switch states • The most common types of FFs are SR, D, JK, and T .

    14. SR Flip Flop • SR flip flop has two states: • Set state when Q=1and Q’=0 • Reset state whenQ=0and Q’=1 • Called active-high. No Change Reset state Set state Indeterminate (internal timing)

    15. SR Flip-Flop • Characteristic table: • Characteristics equation: Q(t+1)=S+R` Q(t) S Clk R

    16. SR Flip-Flop • Timing diagram example( rising edge): Clock S R Q

    17. D Flip-Flop • Drawback of SR ff: it has undesirable condition. • Solution Ensure that inputs S and R are never equal to 1 at the same time. • Modify SR ff with one data input D: • The D input goes directly to the S input. • Its complement D’ is applied to R input. • Drawback of D ff: it does not have a “no change “ condition • Characteristic table: • Characteristic equation: Q(t+1) = D

    18. D Flip-Flop • Block diagram:

    19. D Flip-Flop • Timing diagram example( rising edge): Clock D Q

    20. JK Flip-Flop • The indeterminate condition of the SR type is defined in the JK type. • It can set/reset/complement the output. • Characteristics table: • Characteristics equation: Q(t+1)= JQ’+K’Q

    21. JK Flip-Flop • Timing diagram example( rising edge): Clock J K Q

    22. T Flip Flop • ×خ

    23. T Flip-Flop • Timing diagram example( rising edge): Clock T Q

    24. Direct Inputs • Flip Flops will sometimes provide special input terminals for setting or clearing the FF asynchronously. • Direct inputs force FF to a state independently of clock. • The input that sets FF to 1 is called preset or direct set. • The input that resets FF to 0 is called clear or direct reset. • These inputs are useful for bringing the FFs to an initial state prior to its clocked operation.

    25. Excitation Table • In the design process: • We know the transition from the present state to the next state. • Want to find the FF inputs that cause the transition. • To achieve the goal of design we need Excitation Table. • A table that lists the required inputs for a given change of state. D 0 1