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ECE 511: Digital System & Microprocessor. Week. Subject. W1. Digital Logic Review. W2-W3. Microprocessor Architecture & Overview. W3-W6. Microprocessor Instruction Set & Programming. W7-W9. Memory Interfacing. W10-W12. Parallel I/O Interfacing. Course Outline. References.

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Course outline

Week

Subject

W1

Digital Logic Review

W2-W3

Microprocessor Architecture & Overview

W3-W6

Microprocessor Instruction Set & Programming

W7-W9

Memory Interfacing

W10-W12

Parallel I/O Interfacing

Course Outline


References
References

  • J. L. Antonakos, “The 68000 Microprocessor: Hardware and Software Principles & Applications,” 5th Ed., Pearson Prentice-Hall, 2004.

  • C. M. Gilmore, “Microprocessors: Principles & Applications,” 2nd Ed., McGraw-Hill, 1995.

  • A. Clements, “Microprocessor System Design,” PWS-Kent, 1992.


Course evaluation
Course Evaluation

  • Tests x 2 30%

  • Quizzes x 3 20%

  • Mini Projects 50%


If you have problems please contact me
If you have problems, please contact me:

Ahmad Ihsan bin Mohd Yassin

Rm. T2-A13-1A, Dept. of Comp. Eng.

Faculty of Elect. Eng.

UiTM, Shah Alam.

03-55436118, 017-2576295

*Please call before you see me.


Digital logic review part i

Digital Logic Review: Part I

ECE 511: Digital System & Microprocessor.


What we will learn in this session
What we will learn in this session:

  • Review of logic gates.

  • Flip-flops.

  • Decoders.

  • Universal representation of logic gates.



What are gates
What are gates?

  • Gates are:

    • Simple electronic devices.

    • Constructed using transistors.

    • Used to design digital systems.

  • Three Basic Gates:

    • AND

    • OR

    • NOT

  • Basic Gates can be combined into Extended Gates.

  • Usually packed into ICs.



Basic gate and

A

C

AND

B

TRUTH TABLE

A

B

C

0

0

0

1

0

0

0

0

1

1

1

1

Basic Gate - AND

  • The AND gate is similar to multiply operation.


Basic gate or

A

OR

C

B

TRUTH TABLE

A

B

C

0

0

0

1

1

0

1

0

1

1

1

1

Basic Gate - OR

  • The OR gate is similar to add operation.


Basic gate not

TRUTH TABLE

A

B

0

1

NOT

A

B

1

0

Basic Gate - NOT

  • The NOT gate performs the inverse operation.


Extended gates
Extended Gates

  • Combination of basic gates to perform complex functions:

    • NAND

    • NOR

    • XOR

    • XNOR

    • Flip-Flops


Nand gate

TRUTH TABLE

A

B

C

0

1

0

1

1

0

1

0

1

A

1

1

0

A

C

NAND

C

NOT

AND

B

B

NAND Gate

  • Adds NOT after AND gate.

  • AND outputs are inverted  NAND (NOT-AND).


Nor gate

A

A

C

OR

NOT

C

NOR

B

B

TRUTH TABLE

A

B

C

0

1

0

1

0

0

0

0

1

1

1

0

NOR Gate

  • Adds NOT after OR gate.

  • OR outputs are inverted  NOR (NOT-OR).


Xor gate

A

XOR

C

B

TRUTH TABLE

A

B

C

0

0

0

1

1

0

1

0

1

1

1

0

XOR Gate

  • XOR performs the Exclusive Or operation.

  • When A=B, C=0; when A≠B, C=1.


Xnor gate

A

XOR

B

TRUTH TABLE

A

B

C

0

1

0

1

0

0

A

0

0

1

C

XOR

NOT

C

B

1

1

1

XNOR Gate

  • Adds NOT after XOR gate.

  • XOR outputs inverted  XNOR (NOT XOR).



Flip flops1
Flip-Flops

  • An extended gate used as memory:

    • Each FF stores 1 bit.

  • 2 gates, feedback connections.

  • 2 inputs, 2 outputs.

  • More complex ones may:

    • Use timing from CLK.

    • Perform bit toggle.


Reset set rs flip flop
Reset-Set (RS) Flip-Flop

  • 4 states:

    • Three stable (Set, Reset, and Keep).

    • One not stable (Unused).

  • 2 inputs, 2 outputs.

  • May also contain clock (CLK) signal.


Rs flip flop
RS Flip-Flop

RSFF

R

Q

*Assuming initial condition:

S = 0, R = 0, Q = 0

S

Q’

Qprev

S

R

Q

Q’

KEEP: Output unchanged

N/A

0

0

0

1

SET: Output set (Q = 1)

0

1

0

1

0

RESET: Output reset (Q = 0)

1

0

1

0

1

*As long as S=0 and R=0,

Q will always remain at previous state.

Doesn’t

matter

1

1

N/A

N/A

Unstable


Clocked rs flip flop
Clocked RS Flip-Flop

RSFF

R

Q

*Assuming initial condition:

S = 0, R = 0, Q = 0

CLK

Qprev

S

R

CLK

Q

Q’

S

Q’

KEEP: Output unchanged

N/A

0

0

0

1

0

Doesn’t

matter

Doesn’t

matter

0

1

Only active when CLK

is ↑

SET: Output set (Q = 1)

0

1

0

1

0

RESET: Output reset (Q = 0)

1

0

1

0

1

Reduced sensitivity to noise.

Doesn’t

matter

1

1

N/A

N/A

Unstable


Jk flip flop

Qprev

J

K

Q

Q’

N/A

0

0

0

1

Output unchanged

0

1

0

1

0

Output set (Q = 1)

1

0

1

0

1

Output reset (Q = 0)

Q

1

1

Q

Q

Toggle

JK Flip-Flop

  • Same as RS, but forbidden state used to toggle bit.

  • Can also be clocked using CLK.

*Assuming initial condition:

J = 0, K = 0, Q = 0


Jk flip flop1

Qprev

S

R

Q

Q’

N/A

0

0

0

1

Output unchanged

0

1

0

1

0

Output set (Q = 1)

1

0

1

0

1

Output reset (Q = 0)

Q

1

1

Q

Q

Toggle

JK Flip-Flop

J

Q

K

Q

*Assuming initial condition:

J = 0, K = 0, Q = 0


Clocked jk
Clocked JK

J

Q

CLK

K

Q

Qprev

S

R

CLK

Q

N/A

0

0

0

Output unchanged

0

Doesn’t

matter

Doesn’t

matter

0

Only active when CLK

is ↑

0

1

0

1

Output set (Q = 1)

1

0

1

0

Reduced sensitivity to noise.

Output reset (Q = 0)

Q

1

1

Q

Toggle


D flip flop
D-Flip-Flop

  • Data latch.

  • Modification of RSFF.

  • Stores 1-bit of information.

    • Can be combined to store more.

  • Data are stored in memory using millions of DFFs.


D flip flop1
D-Flip-Flop

DFF

D

Q

EN

Q’

Qprev

D

EN

Q

Q’

QPREV

Doesn’t

Matter

0

QPREV

Q’PREV

*Only active when EN

is 1

Doesn’t Matter

1

1

1

0

Output set (Q = 1)

Doesn’t Matter

0

1

0

1

Output reset (Q = 0)



Storing 8 bits using dff ram
Storing 8-bits using DFF (RAM)

Data Bus

D0

D1

D2

D3

D4

D5

D6

D7

DFF

DFF

DFF

DFF

DFF

DFF

DFF

DFF

EN

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7


Asynchronous latch
Asynchronous Latch

  • Allows both synchronous & asynchronous operations:

    • Synchronous: CLK driven (Clocked JK).

    • Asynchronous: similar to RSFF.

  • 5 inputs, 2 outputs:

    • J, K and CLK for synch. operation.

    • PR, CLR for asynch. operation.


Asynchronous latch1

PRE(S)

J

Q

PRE

CLR

Q

CLK

0

0

Follows J, K, CLK (Synch. JK)

K

Q

0

1

Q = 0, resets output.

1

0

Q = 1, sets output.

1

1

Not valid.

CLR(R)

Asynchronous Latch



Nand and nor as universal gates
NAND and NOR as Universal Gates

  • In industry, NAND and NOR gates are most common.

  • Reason?

    • Can be used to represent any gate (functionally complete).

    • Easiest & cheapest to produce.








Decoder
Decoder

  • A digital circuit that detects a specific combination of input bits (code), and indicates the presence of the code by a specific output.

  • Typically has n inputs and 2n outputs, but other combinations also exist.

  • However, the number of inputs is always less than the outputs (noInputs < noOutputs).

  • Each combination of inputs will generate a unique pattern at the output.


Example active high 2 4 decoder

2-4

Decoder

Y0

I0

Y1

Y2

I1

Y3

Example: Active High 2-4 Decoder

I1

I0

Y3

Y2

Y1

Y0

0

0

0

0

0

1

0

1

0

0

1

0

1

0

0

1

0

0

1

1

1

0

0

0

A specific pattern

at the inputs.

Will activate a

specific bit

at the outputs.


Example active low 2 4 decoder

2-4

Decoder

Y’0

I0

Y’1

Y’2

I1

Y’3

Example: Active Low 2-4 Decoder

I1

I0

Y’3

Y’2

Y’1

Y’0

0

0

1

1

1

0

0

1

1

1

0

1

1

0

1

0

1

1

1

1

0

1

1

1

A specific pattern

at the inputs.

Will activate a

specific bit

at the outputs.


Example active high 3 8 decoder
Example: Active High 3-8 Decoder

A

B

C

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

0

0

0

1

0

0

1

0

0

0

0

0

0

1

0

0

0

1

1

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

0

1

0

0

1

0

0

0

0

0

1

1

0

0

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0


Example active low 3 8 decoder
Example: Active Low 3-8 Decoder

A

B

C

Y7’

Y6’

Y5’

Y4’

Y3’

Y2’

Y1’

Y0’

0

0

0

1

1

1

1

1

1

1

0

0

0

1

1

1

1

1

1

1

0

1

0

1

0

1

1

1

1

1

0

1

1

0

1

1

1

1

1

1

0

1

1

1

1

0

0

1

1

1

0

1

1

1

1

1

0

1

1

1

0

1

1

1

1

1

1

1

0

1

0

1

1

1

1

1

1

1

1

1

0

1

1

1

1

1

1

1


Encoder vs decoder
Encoder vs. Decoder

8  3 Encoder

I0

I1

I2

Y2

I3

Y1

I4

Y0

I5

I6

I7

I0

I1

I2

I3

I4

I5

I6

I7

Y0

Y1

Y2

1

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

0

0

0

1

0

0

0

0

1

0

0

0

0

0

1

1

0

0

0

0

1

0

0

0

1

0

0

0

0

0

0

0

1

0

0

1

0

1

0

0

0

0

0

0

1

0

1

1

0

0

0

0

0

0

0

0

1

1

1

1


Encoder vs decoder1
Encoder vs. Decoder

3  8 Decoder

I0

I1

Y2

I2

Y1

I3

Y0

I4

I5

I6

I7

Y0

Y1

Y2

I0

I1

I2

I3

I4

I5

I6

I7

0

0

0

0

0

0

0

0

0

0

1

0

0

1

0

0

0

0

0

0

1

0

0

1

0

0

0

0

0

0

1

0

0

0

1

1

0

0

0

0

1

0

0

0

1

0

0

0

0

0

1

0

0

0

0

1

0

1

0

0

1

0

0

0

0

0

1

1

0

0

1

0

0

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0


What goes on inside a decoder

Y0

I0 = Y0Y1Y2

Y1

I1 = Y0Y1Y2

I2 = Y0Y1Y2

Y2

I3 = Y0Y1Y2

I4 = Y0Y1Y2

I5 = Y0Y1Y2

I6 = Y0Y1Y2

I7 = Y0Y1Y2

What Goes on Inside a Decoder?


Decoders1
Decoders

  • In this subject, you need to familiarize yourself with two types of decoders:

    • 74LS139 Dual 2-4 Line Decoder.

    • 74LS138 3-8 Line Decoder

  • Decoders are used to:

    • Activate devices for use by µP.

    • Memory, I/O interfacing.


74ls139 dual 2 4 line decoder
74LS139 Dual 2-4 Line Decoder

  • Motorola active low 2-4 decoder.

  • 2 x decoders in one IC.

  • 16 pins total:

    • 2 x (2 inputs, 4 outputs).

    • Vcc (±5V) and GND.

    • 2 x Enable pins.


74ls139 dual 2 4 line decoder1

O0a

O0b

Ea

Eb

O1a

O1b

A0a

A0b

O2a

O2b

A1a

A1b

O3a

O3b

74LS139 Dual 2-4 Line Decoder


74ls139 truth table

E

I1

I0

O3

O2

O1

O0

1

X

X

1

1

1

1

0

0

0

1

1

1

0

0

0

1

1

1

0

1

0

1

0

1

0

1

1

0

1

1

0

1

1

1

74LS139 Truth Table


74ls138 3 8 line decoder
74LS138 3-8 Line Decoder

  • Motorola 3-8 active low decoder.

  • 1 x decoder in one IC.

  • 16 pins total:

    • 3 inputs, 8 outputs (active low).

    • Vcc (±5V) and GND.

    • 3 x Enable pins.


74ls138 3 8 line decoder1

E1

O0

E2

O1

E3

O2

O3

A0

O4

A1

O5

A2

O6

O7

74LS138 3-8 Line Decoder


E1

E2

E3

I2

I1

I0

O7

O6

O5

O4

O3

O2

O1

O0

1

X

X

X

X

X

1

1

1

1

1

1

1

1

X

1

X

X

X

X

1

1

1

1

1

1

1

1

X

X

0

X

X

X

1

1

1

1

1

1

1

1

0

0

1

0

0

0

1

1

1

1

1

1

1

0

0

0

1

0

0

1

1

1

1

1

1

1

0

1

74LS138 Truth Table

0

0

1

0

1

0

1

1

1

1

1

0

1

1

0

0

1

0

1

1

1

1

1

1

0

1

1

1

0

0

1

1

0

0

1

1

1

0

1

1

1

1

0

0

1

1

0

1

1

1

0

1

1

1

1

1

0

0

1

1

1

0

1

0

1

1

1

1

1

1

0

0

1

1

1

1

0

1

1

1

1

1

1

1



Conclusion1
Conclusion

  • Gates: most basic elements in circuits.

  • Gates can be extended to perform advanced functions.

  • Some types are universal (NAND, NOR).


Conclusion2
Conclusion

  • Flip-flops can store data – feedback:

    • Can store previous data.

  • Decoders transform code into original signals.

    • Used in memory interfacing (Chapter 4).



Tutorial1
Tutorial

  • Name the three basic gates.

  • What are extended gates? What’s the difference between extended gates and basic gates?

  • What is the flip-flop used for?


Tutorial2
Tutorial

  • Describe the RS, JK, D and Asynchronous flip-flops and draw the truth tables for them.

  • Why are NAND and NOR gates called universal gates? Why are they special?


Tutorial3
Tutorial

  • Give the definition of decoder.

  • Draw the truth table of the 74LS138 and 74LS139 decoder.



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