A Strange Counter

1. QC QA+ DB DC QA QB D Q D Q D Q clk Clock QA 0 0 1 0 0 1 1 1 0 1 1 0 QB QC 1 0 0 1 0 0 State 000 State 011 State 110 State 011 State 110 State000 A Strange Counter

2. A Strange Counter (Redrawn) CombinationalFeedback Logic DA QA D Q NextState DB QB CurrentState (Output) D Q DC QC D Q clk

3. CurrentState Comb.LogicFor Outputs State FlipFlops Outputs Clock CombinationalLogic For Next State A Generalized Synchronous Circuit NextState • Outputs may be: • The state itself • Some function of the state The number of possible states is 2n, where n is the number of FlipFlops.

4. Current State FF Inputs Next State DA=QB+QC QA QB QC DA DB DC QA+ QB+ QC+ DB=QAQB 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 DC=QB+QA 0 0 1 1 1 0 1 1 0 0 1 0 DA QA D Q 1 1 0 1 1 0 0 1 1 0 1 1 0 1 1 clr 1 0 0 1 1 0 1 1 0 1 0 1 DB 1 0 0 1 0 0 QB 1 1 0 D Q 1 0 0 1 0 0 1 1 1 clr DC QC D Q clr reset clk Analyzing a counter QAQBQC 001 000 011 010 110 111 101 100

5. Step 1: Derive the State Transition Diagram Count sequence: 000, 011, 100, 101, 010, 001,000,… 000 011 Current State Next State 001 QA QB QC QA+ QB+ QC+ 100 0 1 1 0 0 0 010 0 0 0 0 0 1 101 0 0 1 0 1 0 1 0 0 0 1 1 1 0 1 1 0 0 0 1 0 1 0 1 X X X 1 1 0 X X X 1 1 1 Custom Counters Step 2:State Transition Table Note the Don't Care conditions

6. Current State Next State FF Inputs QA QB QC QA+ QB+ QC+ DA DB DC 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 1 0 1 1 0 1 1 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 1 0 1 0 0 1 1 0 X X X 1 0 1 1 1 1 X X X 0 1 0 X X X X X X Custom Counter: Mapping to D FFs Step 3:Choose Flipflop Type for Implementation Figure out FF inputs that will cause appropriate state change For D FF’s next state is just the D input: Q+ D Next State Functions with D FF’s

7. DA DC DB C C C GND C C C B 0 0 0 1 1 1 Pre A AB AB AB C D Q 00 00 00 C’ Clr Reset A 01 01 01 B B B A’ GND B’ 11 11 11 Pre B A A A 1 1 0 0 0 0 C’ D Q 10 10 10 A Clr 1 0 0 1 0 0 C X X X X X X GND Pre C C’ D Q 1 1 0 1 0 0 Clr Custom Counter: Finishing Step 4:Make K-maps for each flipflop input and find final functions DA=AC’ + BC DB=A’B’C’ + AC DC= C’

8. Current State Next State FF Inputs QA QB QC QA+ QB+ QC+ TA TB TC 0 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 1 1 0 1 1 1 1 1 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 1 1 1 1 0 0 1 1 0 X X X 1 0 1 1 1 1 X X X 0 1 0 X X X X X X Custom Counter: Remapping to T FFs Step 3:Choose Flipflop Type for Implementation Figure out FF inputs that will cause appropriate state change 0 1 1 For T FF’s, we have to look at the current state and the next.If the next state is different from the current, then we must toggle (T=1). Next State Functions with T FF’s

9. TA TB TC C C C GND C C C 0 0 0 1 1 1 B Pre A AB AB AB A T Q 00 00 00 C Clr Reset 01 01 01 B B B GND A’ 11 11 11 Pre B C’ A A A 1 0 1 0 1 0 T Q B 10 10 10 A Clr 0 1 1 1 1 1 C X X X X X X GND Pre C ‘1’ 1 0 0 1 1 1 T Q Clr Finishing with Toggle FFs Step 4:Make K-maps for each flipflop input and find final functions TA=C(A+B) TB= A’C’ + B + AC TC=1

10. A B F C E D 000 011 001 100 010 101 VHDL Counters LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY cnt IS PORT(clk: IN STD_LOGIC; reset: IN STD_LOGIC; z: OUT STD_LOGIC_VECTOR(2 downto 0)); END cnt; ARCHITECTURE behavior OF cnt ISType state_type is (A,B,C,D,E,F); SIGNAL state: state_type;BEGIN PROCESS(reset,clk) BEGIN if (reset=‘1’) then state <= A; z <=“000”; elsif (rising_edge(clk))then case state is when A=> state <= B; z <= "011"; when B=> state <= C; z <= “100"; when C=> state <= D; z <= "101"; when D=> state <= E; z <= “010"; when E=> state <= F; z <= “001"; when F=> state <= A; z <= "000"; END CASE; end if; end process; END behavior; Declare possible states (A-F is six states) Asynchronous reset to 000 Here’s the counter…