XFEL Large Pixel Detector DAQ. Project Team. Technical Team: STFC Rutherford DAQ Glasgow University Surrey University Science Team: UCL Daresbury Bath University others …. Project Outline. 1) Phase 1: Develop a digitising pipelined XFEL detector (1k by 1k pixels)
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4 x 4 Super Modules
Sequencing and control
Dynamic range stages
IO to DAQ
Store in Pipeline during bunch train
Readout during long gap
Deep pipeline memory (786,432 samples)
Power supply Conditioning
Data Sampling to Memory
Serialise and Transmit to DAQ
Electron bunch trains; up to 3000 bunches in 600 msec, repeated 10 times per second.
Producing 100 fsec X-ray pulses (up to 30 000 bunches per second).
XFEL ~ 30 000 bunches/s
99.4 ms (%) emptiness
Inner barrel layer
Module Support Cards (MSC) : FPGA Gain Selection
FEMs : Firmware
Switch Inputs / Farm
COTS : FPGA Dev Boards
Xilinx Virtex 5 + EDK PPC
COTS : FPGA-> PC cores (Qx UDP)
Electrical LVDS Links
3 Year Plan includes only elements local to detector.
1 M Pixels x 512 x ~ 2 bytes x 10 Hz ~ 10 GBytes/sec
Fixed length fragments?
Data Selection, Sparsification?
=> 1 TeraByte recorded every 2 minutes !
Each FEM Fragment = 128 KB (64 MB / train)
128 KB x 512 x 10 = 640 MB/s @ 80 MB/s link = 8 links / FEM
Advanced TeleComms Architecture
COTS Carriers + AMC Mezzanines
E.g. ATCA crate for Surface & Nuclear Science
AGATA Daresbury & Padova
ATCA card with
FPGA->PC PCIe readout
6 TB SFPDP Disk Storage