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Security System Using VHDL

Security System Using VHDL. Project Members. Amal Shanavas Aneez I Ijas Rahim Renjith S Menon Sajid S Chavady. Introduction to VHDL. VHDL-abbreviation of Very high speed integrated circuit Hardware Description Language

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Security System Using VHDL

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  1. Security System Using VHDL

  2. Project Members Amal Shanavas Aneez I Ijas Rahim Renjith S Menon Sajid S Chavady

  3. Introduction to VHDL VHDL-abbreviation of Very high speed integrated circuit Hardware Description Language VHDL resulted from the work done in the ‘70s and early ‘80s by the U.S Department of Defense. In 1986,VHDL was proposed as an IEEE standard Its roots are in the ADA language

  4. Why Use VHDL Semiconductor devices dimensions have shrunk Reduces design time for a large digital system because designer can model the circuit in a program that simulates the circuit operation Avoids glitch which occurs in digital circuits Unlike other programs its statements are inherently concurrent To create sophisticated electronic products

  5. Basic Building Blocks ENTITY It is the most basic building block in a design Entity block describes the interface for the design which defines input and output logic signals of the circuit.

  6. Basic Building Blocks ARCHITECTURE All entity that can be simulated have an architecture description The architecture describes the internal operation of the design Single entity can have multiple architectures Three types: : Behavioral Modeling : Structural Design : Sequential behavior

  7. How To Write VHDL Program Active-HDL 4.2 software has been used for the design synthesis and simulation The source code written using the normal TEXT editor,then saved as a VHDL file with '.vhd'extension and transferred to any of the VHDL design compiler.If the compilation shows no error(s),the file can be simulated,synthesized and implemented with FPGA

  8. Circuit Diagram High-level

  9. Voltage regulator Temperature Sensor Relay Voltage Cut off Board

  10. Source Code library IEEE; use IEEE.STD_LOGIC_1164.all; ENTITY alarm_cntrl is port(fire,temperature,alarm_disable,main_disable:in STD_LOGIC; fire_alarm:OUT STD_LOGIC); END alarm_cntrl; architecture synth of alarm_cntrl is begin process(fire,temperature,alarm_disable,main_disable) begin if ((fire='1')and (main_disable='0'))then fire_alarm<='1'; else fire_alarm<='0'; end if; end process; end synth;

  11. Block Diagram-SENSOR Voltage regulator Temperature Sensor Relay Voltage Cut off Board To Ports

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