MTD Readout Electronics. J. Schambach University of Texas Hefei, March 2011. TOF Electronics Overview. The same as TOF, mostly…. THUB , TCPU , TDIG are identical Each TCPU reads out 3 or 5 TDIG (1 backleg ) MINO is a 4- NINO version of TINO
University of Texas
Hefei, March 2011
FIFO orDual port RAM
FIFOHPTDC: Data driven TDC
Coarse time(bin width 25 ns, 11 bits)
(bin width 3.125 ns)
(bin width 98 ps)
(bin width 24.4 ps)HPTDC Time Measurement
HPTDC is fed by a 40 MHz clock giving us a basic 25 ns period (coarse count).
A PLL (Phase Locked Loop)
deviceinside the chip does clock multiplication by a factor 8 (3 bits) to 320 MHz (3.125 ns period) .
ADLL (Delay Locked Loop)
done by 32 cells fed by the PLL clock acts as a 5 bit hit register for each PLL clock (98 ps width LSB = 3.125 ns/32).
4R-C delay lines
divide each DLL bin in 4 parts (R-C interpolation)
8 channel @ 25ps
32 channels @ 100ps
National’s SerDes Chip