Design guidelines for EMC of Components

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Design guidelines for EMC of Components. Summary. Which problems? EMC Guidelines at PCB level IC Guidelines for low emission IC Guidelines for low immunity Starcore case study. October 14. EMC guidelines. Which problems? Know your enemy. Power integrity (PI). Signal integrity (SI).

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Design guidelines for EMC of Components

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1. Design guidelines for EMC of Components

2. Summary Which problems? EMC Guidelines at PCB level IC Guidelines for low emission IC Guidelines for low immunity Starcore case study October 14

3. EMC guidelines Which problems? Know your enemy Power integrity (PI) Signal integrity (SI) ESD, EFT, EOS Conducted emission (CE) Integrated circuits / electronic applications Radiated emission (RE) Radiated immunity (RI) Conducted immunity (CI) October 14

4. EMC guidelines at PCB level Signal integrity (SI) issue • Example: voltage measurement at 3 terminals of two 20 cm long parallel PCB tracks. • The first line is excited by a pulse generator, the second is terminated by two resistive loads. Origin of effects on both lines ?

5. EMC guidelines at PCB level Signal integrity (SI) issue • Let’s consider a transmission along two conductors = 2-conductor transmission line. Let’s suppose an homogeneous lossless line • Equivalent model: z 0 L ZG I(z,t) + + + + + + Interconnect ZL VG - - - - - - - I(z,t) Thevenin generator Transmission line Load • The voltage and current on each point of the line is superposition of a forward and backward voltage, travelling in opposite directions.

6. EMC guidelines at PCB level Signal integrity (SI) issue • The voltage at each point of the line depends on the reflection coefficient at each line terminals: • Transient behavior of voltage at each line terminals: At generator side (input): At generator side (input): Complex transient behavior related to the reflection coefficient on each extremities and transmission line discontinuities October 14

7. EMC guidelines at PCB level Vsource Vload Overshoot / Undershoot Overshoot / Undershoot t t 0 0 4L/v 3L/v 2L/v L/v Signal integrity (SI) issue • Analysis of the round-trip period of the wave along the line Time (ns) Source Load 0 VL(0)=0V L/v 2L/v 7 October 14

8. EMC guidelines at PCB level Signal integrity (SI) issue Zc ; Tp VL VG Criterion for SI issue: Overshoot VL or VG if Tr is the rising or falling time of a signal, SI issues due to the propagation of the EM wave along the transmission line arise if: Vdd VIH Undetermined level Undershoot VIL Ringing 0 t Longer setting time October 14

9. EMC guidelines at PCB level Ensuring Signal integrity – Rule 1 Cancel reflection coefficient at each line terminals by impedance matching Impedance matching of a uniform transmission line with constant characteristic impedance Zc. • Practical designs for a digital transmission: Vcc Zc Zc Rs Rpd Rpd Ct Rs : serial resistor= Rdriver - Zc Rpd : pull down resistor = Zc October 14

10. EMC guidelines at PCB level Ensuring Signal integrity – Rule 2 Control the characteristic impedance of (2-conductor) transmission line (PCB track, package)  avoid line discontinuities • Microstrip line configuration: W εr I t h Ideal ground plane Is it better to use wide or narrow trace ? October 14

11. EMC guidelines at PCB level Ensuring Signal integrity – Rule 3 Ensure a controlled and short return current path. • Place a full ground plane in microstrip line. • Avoid slot in return plane (e.g. ground plane) • Keep a symmetry (avoid unbalance in the return current path) CORRECT BAD October 14

12. EMC guidelines at PCB level Ensuring Signal integrity – Rule 3 • Example: a microstrip line routed over 2 separated power planes. SI design rule violation From ECST Broadcheck – www.cst.com October 14

13. EMC guidelines at PCB level • Equivalent model: RL Emitter trace RS Capacitive coupling VE RNE RFE Far end Victim trace Near end VNE VFE Signal integrity (SI) - Crosstalk • Let’s consider 2 traces separated by a distance d. Inductive coupling Trace 1 (emitter) Trace 2 (victim) d V W W I1’ CM LM I1 Crosstalk (near-field coupling) εr I2 h Parasitic return current path “Normal” return current path 13 October 14

14. EMC guidelines at PCB level Signal integrity (SI) - Crosstalk • Low frequency model (quasi-static approximation  propagation effects neglected) VNE VFE Validity of quasi-static approximation 14 October 14

15. EMC guidelines at PCB level Ensuring Signal integrity – Rule 4 Increase the isolation between emitter and victim lines • Increase the distance between traces (rule 3 W = “the separation between traces must be 3 times the width of the trace as measured from centerline to centerline of two adjacent traces”) < 3W W W t (εr = 4.5) h Substrate ground 15 October 14

16. EMC guidelines at PCB level Power integrity (PI) issue – Power Distribution Network Bulk capacitor (Low frequency) HF capacitor (ceramic) PCB – Power / ground plane Package and IC Power source Voltage converter / regulator Ferrite Vdd Vss 1 µF – 10 mF Ground reference 100 nF – 1 nF 1 nF Transistors, gates, interconnects 16 October 14

17. EMC guidelines at PCB level Power integrity (PI) issue Power supply source (regulator, DC-DC converter) PDN ΔVdd Noisy Integrated circuit Vdd PDN i(t) ΔVss Vss Circuit Power supply bounce Delta-I noise 17 October 14

18. EMC guidelines at PCB level Power integrity (PI) issue • Example: on-chip measurement of the power supply voltage fluctuation of a digital circuit Low frequency contribution High frequency contribution Switching Switching Switching Noise with a large frequency content and some major resonance modes 18 October 14

19. EMC guidelines at PCB level Power integrity (PI) issue • Equivalent model of a PDN (the most basic model…) PDN Circuit Vdd Power supply voltage bounce: ZPDN ΔVdd IIC gnd • Ensuring power integrity relies on the control of a low impedance of the PDN. • A target impedance ZT can be defined as a design objective: ZPDN Zt Frequency Target frequency range 19 October 14

20. EMC guidelines at PCB level Ensuring Power integrity – Rule 1 Reduce interconnect parasitic (mainly inductance) of power and ground connections • Use traces as wide as possible for Vdd and Vss connections • i.e. use power and ground planes • Be careful of the common impedance of Vdd and Vss connections (finite impedance, even for ground plane): Single point grounding with serial circuits Direct grounding to a reference ground plane 20 October 14

21. EMC guidelines at PCB level Local charge tank In time domain In frequency domain Large capacitors reduce PDN impedance. Large capacitors react rapidly to charge demand. Ensuring Power integrity – Rule 2 Add decoupling capacitor to reduce power supply bounce as close as possible from noise source (current demand) Voltage bounce v(t) • Principle: Voltage regulator IC Vdd Vss Vdd PCB Vss Decoupling capacitor i(t) 21 October 14

22. EMC guidelines at PCB level 10 – 15 dB Efficient on one decade 10-100 nF decoupling Ensuring Power integrity – Rule 2 • Effect of on-board capacitors: No decoupling X7R 50 V ceramic capacitors Customer’s specification Parasitic emission (dBµV) 80 70 60 50 40 100 µF electrolytic capacitor 30 20 10 0 -10 1 10 100 1000 Frequency (MHz) 22 October 14

23. EMC guidelines at PCB level Ensuring Power integrity – How choosing decoupling capacitor • If ideal capacitor, only one decoupling capacitor would be enough: • Cdec: the minimum capacitor able to provide a current to the circuit without any large voltage fluctuations. • ΔVddmax : max allowed voltage fluctuation • ΔI : current peak absorbed by the circuit • tr : rise time of the current peak • However, due to the parasitic elements associated to decoupling capacitors, its efficiency frequency range is limited or it can not respond to rapid current demand. • It is necessary to place several decoupling capacitors in parallel to increase the efficiency frequency range of the decoupling. 23 October 14

24. EMC guidelines at PCB level Ensuring Power integrity – How choosing decoupling capacitor • Methodology to optimize the choice of decoupling capacitors: Define Zt Board model Regulator model Circuit(s) model PDN without decoupling model Define freq. range of decoupling Fmin Fmax Compute ZPDN YES If ZPDN(f) > Zt for f in [Fmin;Fmax] NO Add capacitor(s) and/or change capa values Capacitors model Power integrity OK – Decoupling budget October 14

25. EMC guidelines at PCB level Ensuring Power integrity – How choosing decoupling capacitor • Example: decoupling of a 16 bit microcontroller (dspic33F). • The circuit produces a significant amount of noise over the range 1 – 500 MHz. • We select Zt = 2 Ω. IC Current (1 Ω probe) Z PDN (VNA measurement) Board + IC without decap ZT With 6×100 nF decap 25 October 14

26. EMC guidelines at PCB level Ensuring Power integrity – Anti-resonance issue • What happens if 2 “real” capacitors are placed in parallel ? Fantires Fantires = 26 October 14

27. EMC guidelines at PCB level Ensuring Power integrity – Anti-resonance issue • Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF X7R decoupling capacitor. • The PDN impedance measurement shows an anti-resonance at 162 MHz PDN equivalent model Fantires What is the cause of this anti-resonance ? October 14

28. EMC guidelines at PCB level Ensuring Power integrity – Anti-resonance issue • Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF X7R decoupling capacitor. • Measurement of power supply voltage in time domain (16 I/O pads switch simultaneously). October 14

29. EMC guidelines at PCB level Ensuring Immunity – Anti-resonance issue • Example: power integrity of a 16 bit microcontroller (dspic33F) with 6×100 nF X7R decoupling capacitor. • Measurement of conducted immunity (harmonic signal coupled on power supply plane according to DPI standard). At each harmonic frequency, the disturbance power is increased until a circuit failure arises. Max. Power

30. EMC guidelines at PCB level Radiated emission – basic mechanisms • Radiated emissions come from interconnects excited by a transient current or voltage. They become parasitic antennas. • Two basic radiated mechanisms: • Dipole antenna (electric) • high impedance load (I/O loaded by high impedance) • E field proportional to length l • Loop antenna (magnetic) • Low impedance load (power supply, I/O loaded by low impedance • H field proportional to surface S Electric field Magnetic field Circuit Circuit I Clock VSS VDD Length l High Z load Surface S 30 October 14

31. EMC guidelines at PCB level Radiated emission – basic mechanisms • Differential vs. common radiated mode. • Common mode appears when the return current path is not perfectly defined. If I1 ≠ I2 I1 Interco 1 Id Differential mode I2 Decomposition in 2 distinct propagation modes Id 1 Interco 2 2 Ic 1 Ic Common mode 31 2 October 14

32. EMC guidelines at PCB level Radiated emission – basic mechanisms • Comparison of common and differential radiated mode. • Let’s consider electrically 2 short parallel interconnects (length L << λ): L=10 cm, d=2 mm, r = 1 m, ID = 50 mA, IC = 5 mA • L: interconnect length • d: interconnect separation • f: frequency of excitation current • r: distance between E field measurement point and interconnect centers • ID and IC: differential and common mode currents • ED and EC: differential and common mode radiation (E field) Main conclusions about radiation mechanisms ? 32 October 14

33. EMC guidelines at PCB level Reducing radiated emission – Rule 1 Reduce parasitic antenna (length or surface) to reduce differntial and common mode radiation • Identify current loops on PCB and reduce their surface. • Place decoupling capacitors as close as possible to IC pins. • Use power or ground plane to reduce current loop surface. • Reduce the length of interconnects which carry high frequency signals. Circuit Circuit VDD VDD Decoupling capacitor VSS VSS Decoupling capacitor Id Id Smaller loop  Reduced radiated differential mode Large loop  High radiated differential mode 33 October 14

34. EMC guidelines at PCB level Reducing radiated emission – Rule 2 Control the current return path to reduce common mode Example 2: one differential output buffer with a non symmetrical routing Example 1: one Vdd pin but two Vss pins IVdd = IVSS1+IVSS2 Power Differential buffer I+ ≠ I- Circuit IVdd I+ VDD D+ VSS2 VSS1 I- D- IVss1 Parasitic coupling GND IVSS2 Ic 34 October 14

35. EMC guidelines at PCB level Reducing radiated emission – Rule 3 Use a “good” ground plane(s) to shield noisy interconnects • Use coplanar or stripline configuration to shield noisy interconnect. • A “good” reference plane is equipotential at any point ! • Connect two reference plane witth same potential by vias regular interval less than λ/20 ! Correct connection between two planes with same potential Stripline configuration Ref plane line GND via Ref plane GND 35 October 14

36. EMC guidelines at PCB level Radiated emission – Case study • Basic digital applications routed on a 2 layer board with the auto-router function of the board design tool. Only one 100 nF decoupling capacitor for all the application. • Measurement of radiated emission in TEM cell. Limit CISPR25

37. EMC guidelines at PCB level Radiated emission – Case study • Numerous EMC design rules violation: large power-ground loops, long fast clock interconnect, return path not ensured by a ground plane… • Change the placement & routing of the board by starting to place Vdd/Vss and fast clock, add a ground plane on both side. • Design rule violation examples: Large loop Vdd connection CMOS inverter Vss connection Equivalent surface of fast clock interconnect “High speed” clock source 37

38. EMC guidelines at PCB level Radiated emission – Case study Top layer Effect of placement & Routing improvement (still one 100 nF decoupling capacitor) -30 dB Bottom layer 38 October 14

39. EMC guidelines at PCB level Radiated emission – Case study Effect of decoupling capacitors (one capacitor per circuit) Effect of GND vias density + or – effect depending on freq. ≈ -5 dB 39 October 14

40. EMC guidelines at PCB level Summary • EMC can be improved at PCB level, mainly by an adequate placement and routing of rapid signals, power and ground references. • Several EMC issues have the same root causes  one EMC design rule can solve several problems. • The modeling is important to understand the problem and optimize solution. • An accurate IC model is mandatory to manage EMC at PCB level. 40 October 14

41. Golden Rules for Low Emission Rule 1: Power supply routing strategy A) Use shortest interconnection to reduce the serial inductance • Inductance is a major source of resonance • Each conductor acts as an inductance • Ground plane modifies inductance value (worst case is far from ground) Reducing inductance decreases SSN !! Lead: L=0.6nH/mm Bonding: L=1nH/mm October 14

42. Golden Rules for Low Emission Rule 1: Power supply routing strategy A) Use shortest interconnection to reduce the serial inductance Leadframe package: L up to 10nH Die of the IC bonding Long leads Far from ground PCB Flip chip package: L up to 3nH Short leads balls Die of the IC Close from ground Requirements for high speed microprocessors : L < 50 pH ! October 14

43. Golden Rules for Low Emission Correct Fail Rule 1: Power supply routing strategy B) Place enough supply pairs: Use One pair (VDD/VSS) for 10 IOs 9 I/O ports October 14

44. Golden Rules for Low Emission Current density simulation Layout view VDD / VSS VDD / VSS VDD / VSS Rule 1: Power supply routing strategy C) Place supply pairs close to noisy blocks Memory PLL Digital core October 14

45. Golden Rules for Low Emission EM field Current loop Added contributions Reduced contributions EM wave EM wave current current Die Lead Lead currents Rule 1: Power supply routing strategy D) Place VSS and VDD pins as close as possible • to increase decoupling capacitance that reduces fluctuations • to reduce current loops that provoke magnetic field October 14

46. Golden Rules for Low Emission Rule 1: Power supply routing strategy Case study 2: Case 1 : Infineon Tricore Case 2 : virtex II Worst case not enough supply pairs, bad distribution & dissymmetry Not ideal Not enough supply for IOs : (core emission is lower than IO one) October 14

47. Golden Rules for Low Emission Rule 1: Power supply routing strategy Case study 2: 2 FPGA , same power supply, same IO drive, same characteristics Supply strategy very different ! • More Supply pairs for IOs • Better distribution courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com October 14

48. Golden Rules for Low Emission Rule 1: Power supply routing strategy Case 1: low emission due to a large number of supply pairs well distributed Case 2: higher emission level (5 times higher) courtesy of Dr. Howard Johnson, "BGA Crosstalk", www.sigcon.com October 14

49. Golden Rules for Low Emission Rule 1: Power supply routing strategy 324-BGA (49 Vdd/Vss pairs) 208-BGA (31 Vdd/Vss pairs) Case study 3:conducted (150 ohms probe placed on Vdd) and radiated (TEM cell) emission from a microcontroller mounted in either & 208-BGA or a 324-BGA. • Larger conducted emission from 208-BGA (less power supply pins) • Larger radiated emission from 324-BGA (larger interconnects) E. Rogard and al., "Characterization and Modelling of Parasitic Emission of a 32-bit Automotive Microcontroller Mounted on 2 Types of BGA", IEEE EMC Symposium Austin, Texas, USA 2009 October 14

50. Golden Rules for Low Emission Rule 2: Add decoupling capacitance On chip decoupling capacitance versus technology and complexity: Intrinsic on-chip supply capacitance 65nm 100nF 90nm 0.18µm 10nF 0.35µm 1.0nF 100pF Devices on chip 10pF 100K 1M 10M 100M 1G Example: in 65nm technology, for a 200 Million devices on chip the intrinsic capacitance is 10nF October 14