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Itanium Architecture - PowerPoint PPT Presentation

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Itanium Architecture
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  1. Itanium Architecture • The History of Intel’s 32-bit(IA-32) processors. • Overview of Itanium(IA-64) with respect to Intel’s 32-bit(IA-32) Processors • Future of the Itanium and IA-32 processors.

  2. The History of the Intel’s 32-bit(IA-32) Processors. • 386 - First 32-bit Intel processor - It introduced 32-bit registers for operands and addressing - Backward compatible • 486 - Parallel Execution Capabilities - Integrated FPU. • Pentium - Two Execution Pipelines - MMX and Level 1 cache. • Pentium Pro - Three Execution Pipelines - Introduced the concept of Dynamic Execution - Level 2 cache.

  3. Pentium II/PII Xeon - No major Architecture improves just larger L1 and L2 cache sizes. • Pentium III/PIII Xeon - L2 Cache placed on the die to run at same speed as processor. - Streaming SIMD Extension(SSE) Allows one instruction to perform the same function on several pieces of data simultaneously. • Celeron - No Architecture improves, just cheaper to produce. • Pentium IV introduces NetBurst Micro-Architecture - Rapid Execution Engine - Hyper Pipelined Technology - Advanced Dynamic Execution - New Cache Subsystem

  4. Overview of Itanium(IA-64) with respect to Intel’s 32-bit(IA-32) Processors • Integer/Floating Point Registers • IA-32: has only 8 registers • IA-64: has 128 registers • Addressable Memory • IA-32: 32-bit can address up to 4GB of memory. • IA-64: 64-bit can address up to 16TB of memory. • CISC or Complex Instruction Set Computer (IA-32) • Large amount of complex Instructions • Newer CISC processors try to process more than one instruction at a time. But to do this they have to analyze and re-order instructions. • EPIC or Explicitly Parallel Instruction Computing (IA-64) • Three 41-bit instructions are fetched and processed in parallel • Software can communicate explicitly with the processor when operations can be performed in parallel.

  5. Future of the Itanium(IA-64) and IA-32 processors • IA-32 • Intel say that IA-32 processors will be around for a long time to come. Say the Itanium is mainly going to be for high end business and scientific computing. • HP/Intel Grant $2.5 Million In Itanium based Systems • HP and Intel sent 40 universities worldwide Itanium Workstations • TeraGrid • National Science Foundation(NSF) awarded Intel $53 million. To build a Distributed Terascale Facility(DTF). The Grid will contain 3300 Intel Itanium family processors. Which will be capable of more than 13.6 trillion calculations per second. (13.6 teraflops). It will also have access to 450TBs.