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Computer Organization and Architecture Lecture 5 COMPUTER ARITHMETICS. Huma Ayub. Department of Software Engineering. University of Engineering and Technology Taxila. 1. Arithmetic. Where we've been: Performance (seconds, cycles, instructions)

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## Computer Organization and Architecture Lecture 5 COMPUTER ARITHMETICS

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**Computer Organization and Architecture**Lecture 5 COMPUTER ARITHMETICS Huma Ayub Department of Software Engineering. University of Engineering and Technology Taxila 1**Arithmetic**• Where we've been: • Performance (seconds, cycles, instructions) • Abstractions: Instruction Set Architecture Assembly Language and Machine Language • What's up ahead: • Implementing the Architecture**operation**a ALU 32 result 32 b 32 Arithmetic • We start with the Arithmetic and Logic Unit**Numbers**• Bits are just bits (no inherent meaning)— conventions define relationship between bits and numbers • Binary numbers (base 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001... decimal: 0...2n-1 • Of course it gets more complicated: numbers are finite (overflow) fractions and real numbers negative numbers • How do we represent negative numbers? i.e., which bit patterns will represent which numbers? • Octal and hexadecimal numbers • Floating-point numbers**Possible Representations of Signed Numbers**• Sign Magnitude: One's Complement Two's Complement 000 = +0 000 = +0 000 = +0 001 = +1 001 = +1 001 = +1 010 = +2 010 = +2 010 = +2 011 = +3 011 = +3 011 = +3 100 = -0 100 = -3 100 = -4 101 = -1 101 = -2 101 = -3 110 = -2 110 = -1 110 = -2 111 = -3 111 = -0 111 = -1 • Issues: balance, ease of operations. • Two’s complement is best.**maxint**minint MIPS • 32 bit signed numbers:0000 0000 0000 0000 0000 0000 0000 00002 = 0100000 0000 0000 0000 0000 0000 0000 00012 = +1100000 0000 0000 0000 0000 0000 0000 00102 = +210...0111 1111 1111 1111 1111 1111 1111 11102 = +2,147,483,64610 • 0111 1111 1111 1111 1111 1111 1111 11112 = +2,147,483,647101000 0000 0000 0000 0000 0000 0000 00002 = –2,147,483,648101000 0000 0000 0000 0000 0000 0000 00012 = –2,147,483,647101000 0000 0000 0000 0000 0000 0000 00102 = –2,147,483,64610...1111 1111 1111 1111 1111 1111 1111 11012 = –3101111 1111 1111 1111 1111 1111 1111 11102 = –2101111 1111 1111 1111 1111 1111 1111 11112 = –110**Two's Complement Operations**• Negating a two's complement number: invert all bits and add 1 • Converting n bit numbers into numbers with more than n bits: • MIPS 16 bit immediate gets converted to 32 bits for arithmetic e.g addi vs add • copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010 "sign extension" • MIPS load byte instructions lbu: no sign extension lb: sign extension**operation**op a b res 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 1 1 1 1 1 result Logical unit • Let's build a logical unit to support the and and or instructions • we'll just build a 1 bit unit, and use 32 of them • op=0: and; op=1: or a b**S**A C B Operation a 0 1 Result b Review: The Multiplexor • Selects one of the inputs to be the output, based on a control input • Lets build our logical unit using a MUX: 0 1**Different Implementations**• Not easy to decide the “best” way to build something • Don't want too many inputs to a single gate • Don’t want to have to go through too many gates • For our purposes, ease of understanding is important • We use multiplexors • Let's look at a 1-bit ALU for addition:How could we build a 32-bit ALU for AND, OR and ADD? This Circuitry define Boolean equation a b cin cout sum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 CarryIn a Sum b CarryOut cout = a b + a cin + b cin sum = a b cin Sum= a’b’c+a’b c’+a b’c’+abc**Building a 32 bit ALU for AND, OR and ADD**1-bit ALU: We need a 4-input MUX. cout = a b + a cin + b cin sum = a b cin Sum= a’b’c+a’b c’+a b’c’+abc**What about subtraction (a – b) ?**• Two's complement approach: just negate b and add. • A clever solution:**Tailoring the ALU to the MIPS**• Need to support the set-on-less-than instruction (slt) • remember: slt is an arithmetic instruction • produces a 1 if rs < rt and 0 otherwise • use subtraction: (a-b) < 0 implies a < b • Need to support test for equality (beq $t5, $t6, $t7) • use subtraction: (a-b) = 0 implies a = b**Supporting slt**• Other ALUs:**32 bit ALU supporting slt**a<b a-b<0, thus Set is the sign bit of the result.**Final ALU including test for equality**• Notice control lines:000 = and001 = or010 = add110 = subtract111 = slt • Note: Zero is a 1 when • the result is zero!**Partial Products**Multiplication • Basic algorithm analogous to decimal multiplication • Break multiplier into digits • Multiply one digit at a time; shift multiplicand to form partial products • Create product as sum of partial products • n bit multiplicand X m bit multiplier = (n+m) bit product Multiplicand 0110 (6) Multiplier X 0011 (3) 0110 0110 0000 0000 Product 00010010 (18) Multiplication and Division**Multiplicand shifts left**Multiplier shifts right Sample LSB of multiplier to decide whether to add Multiplicand (64 bits) Product (64 bits) Multiplier (32 bits) Shift Left Write Shift Right LSB 64-bit ALU Control Sequential Multiplier - First Version Multiplication and Division**START**1. TestMultiplier0 LSB Multiplier0=1 Multiplier0=0 1a. Add Multiplicandto ProductPlace result in Product 2. Shift Multiplicandleft 1 bit 2. Shift Multiplierright 1 bit 32ndRepitition? DONE Algorithm - 1st Cut Multiplier • Product Multiplier Multiplicand • 0000 0000 0011 0000 0010 • 0000 0010 0001 0000 0100 • 0000 0110 0000 0000 1000 • 0000 0110 Multiplication and Division**Multiplicand**Multiplicand Multiplicand Multiplicand Multiplier Product (64 bits) Write LSB 64-bit ALU Control Animation - 1st Cut Multiplier • Multiplicand shifts left • Multiplier shifts right • Sample LSB of multiplier to decide whether to add Multiplicand Multiplication and Division**Multiplicand**(32 bits) Multiplier (32 bits) Shift Right LSB 32-bit ALU Control Shift Right Product(64 bits) Write Sequential Multiplier - 2nd Version • Observation: we’re only adding 32 bits at a time • Clever idea: Why not... • Hold the multiplicand still and… • Shift the product right! LHPROD (32 bits) RHPROD(32 bits) Multiplication and Division**START**1. TestMultiplier0 Multiplier0=1 Multiplier0=0 1a. Add MCND to left half of ProductPlace result in left half of Product 2. Shift Productright 1 bit 2. Shift Multiplierright 1 bit 32ndRepitition? No: <32 Repititions Yes: 32 Repititions DONE Algorithm - 2nd Version Multiplier Product Multiplier Multiplicand 00000000 0011 0010 00100000 000100000001 0010 001100000001 0010 000110000000 0010 000011000000 0010 00000110 0000 0010 Multiplication and Division**Multiplicand**(32 bits) 32-bit ALU Control Shift Right Product(64 bits) Write LSB Sequential Multiplier - 3nd Version • Observation: we can store the multiplier and product in the same register! • As multiplier shifts out…. • Product shifts in MP/RHPROD(32 bits) LHPROD (32 bits) MPY (initial)(32 bits) Multiplication and Division**START**0. LOAD MPY in right half of PROD 1. TestPROD0 Product0=1 Product0=0 1a. Add MCND to left half of PRODPlace result in left half of PROD 2. Shift PRODright 1 bit 32ndRepitition? No: <32 Repititions Yes: 32 Repititions DONE Algorithm - 3rd Version Multiplier Multiplication and Division

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