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http://www.comp.nus.edu.sg/~cs2100/. Lecture #12. The Processor: Control. Lecture #12: Processor: Control. Identified Control Signals Generating Control Signals: Idea The Control Unit Control Signals ALU Control Signal Instruction Execution. Complete Datapath. Instruction Memory. MUX.

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comp.nus.sg/~cs2100/

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  1. http://www.comp.nus.edu.sg/~cs2100/ Lecture #12 The Processor: Control

  2. Lecture #12: The Processor: Control Lecture #12: Processor: Control • Identified Control Signals • Generating Control Signals: Idea • The Control Unit • Control Signals • ALU Control Signal • Instruction Execution

  3. Complete Datapath Lecture #12: The Processor: Control Instruction Memory MUX Instruction Left Shift 2-bit Address PC PCSrc Add 4 Add ALUcontrol Inst [25:21] 4 5 RR1 RD1 5 MemWrite is0? Inst [20:16] RR2 opcode 31:26 000000 01001 rs 25:21 rt 20:16 01010 rd 15:11 01000 shamt 10:6 00000 funct 5:0 100000 Register File ALU ALUSrc 5 WR ALU result MUX Address MUX RD2 Data Memory MemToReg WD Inst [15:11] Read Data MUX RegWrite RegDst Write Data Sign Extend Inst [15:0] MemRead

  4. Lecture #12: The Processor: Control 1. Identified Control Signals

  5. Lecture #12: The Processor: Control 2. Generating Control Signals: Idea • The control signals are generated based on the instruction to be executed: • Opcode Instruction Format • Example: • R-Format instruction  RegDst = 1 (use Inst[15:11]) ) • R-Type instruction has additional information: • The 6-bit "funct" (function code, Inst[5:0]) field • Idea: • Design a combinatorial circuit to generate these signals based on Opcode and possibly Function code • A control unit is needed (a draft design is shown next)

  6. The Control Unit (draft) Lecture #12: The Processor: Control Instruction Memory MUX Instruction Left Shift 2-bit Address Control PC PCSrc Add 4 Add ALUcontrol Inst [25:21] 4 5 RR1 RD1 5 MemWrite is0? Inst [20:16] RR2 000000 opcode 31:26 rs 25:21 01001 rt 20:16 01010 01000 rd 15:11 00000 shamt 10:6 funct 5:0 100000 Register File ALU ALUSrc 5 WR ALU result MUX Address MUX RD2 Data Memory MemToReg WD Inst [15:11] Read Data MUX RegWrite RegDst Write Data Sign Extend Inst [15:0] MemRead

  7. Lecture #12: The Processor: Control 3. Let’s Implement the Control Unit! • Approach: • Take note of the instruction subset to be implemented: • Opcode and Function Code (if applicable) • Go through each signal: • Observe how the signal is generated based on the instruction opcode and/or function code • Construct truth table • Design the control unit using logic gates

  8. opcode shamt funct 31 25 20 15 10 5 31 25 20 15 Lecture #12: The Processor: Control 3. MIPS Instruction Subset (Review) 016 rs rt rd 0 2016 add sub 016 rs rt rd 0 2216 016 rs rt rd 0 2416 R-type and 016 rs rt rd 0 2516 or 016 rs rt rd 0 2A16 slt 2316 rs rd offset lw 2B16 rs rd offset sw I-type 416 rs rd offset beq

  9. Lecture #12: The Processor: Control 4. Control Signal: RegDst 0 MUX • False (0): Write register = Inst[20:16] • True (1): Write register = Inst[15:11] 1 Signal

  10. Lecture #12: The Processor: Control 4. Control Signal: RegWrite • False (0): No register write • True (1): New value will be written

  11. Lecture #12: The Processor: Control 4. Control Signal: ALUSrc • False (0): Operand2 = Register Read Data 2 • True (1): Operand2= SignExt(Inst[15:0])

  12. Lecture #12: The Processor: Control 4. Control Signal: MemRead • False (0): Not performing memory read access • True (1): Read memory using Address

  13. Lecture #12: The Processor: Control 4. Control Signal: MemWrite • False (0): Not performing memory write operation • True (1): memory[Address]  Register Read Data 2

  14. Lecture #12: The Processor: Control 4. Control Signal: MemToReg 1 MUX • True (1): Register write data = Memory read data • False (0): Register write data = ALU result 0 Signal IMPORTANT: The input of MUX is swapped in this case

  15. Lecture #12: The Processor: Control 4. Control Signal: PCSrc (1/2) • The "isZero?" signal from the ALU gives us the actual branch outcome (taken/not taken) • Idea: “If instruction is a branch AND taken, then…”

  16. Lecture #12: The Processor: Control 4. Control Signal: PCSrc (2/2) • False (0): Next PC = PC + 4 • True (1): Next PC = SignExt(Inst[15:0]) << 2 + (PC + 4) PCSrc = ( Branch ANDisZero)

  17. Lecture #12: The Processor: Control 4. Midpoint Check • We have gone through almost all of the signals: • Left with the more challenging ALUControl signal • Observation so far: • The signals discussed so far can be generated by opcode directly • Function code is not needed up to this point • A major part of the controller can be built based on opcode alone

  18. The Control Unit v0.5 Lecture #12: The Processor: Control Instruction Memory PC MUX Add 4 Instruction Left Shift 2-bit Address PCSrc Control Branch Inst [31:26] Add Inst [25:21] 5 RR1 RD1 5 is0? MemWrite Inst [20:16] RR2 opcode 31:26 rs 25:21 rt 20:16 rd 15:11 shamt 10:6 funct 5:0 Registers ALU ALUSrc 5 WR ALU result MUX Address MUX RD2 Data Memory MemToReg WD Inst [15:11] 4 Read Data ALUcontrol MUX RegWrite RegDst Write Data Sign Extend Inst [15:0] MemRead

  19. Lecture #12: The Processor: Control 5. Closer Look at ALU • The ALU is a combinatorial circuit: • Capable of performing several arithmetic operations • In Lecture #11: • We noted the required operations for the MIPS subset • Question: • How is the ALUcontrol signal designed?

  20. Lecture #12: The Processor: Control 5. One Bit At A Time • A simplified 1-bit MIPS ALU can be implemented as follows: • 4 control bits are needed: • Ainvert: • 1 to invert input A • Binvert: • 1 to invert input B • Operation (2-bit) • To select one of the 3 results Acknowledgement: Image taken from NYU Course CSCI-UA.0436

  21. Lecture #12: The Processor: Control 5. One Bit At A Time (Aha!) • Can you see how the ALUcontrol (4-bit) signal controls the ALU? • Note: implementation for slt not shown Acknowledgement: Image taken from NYU Course CSCI-UA.0436

  22. Lecture #12: The Processor: Control 5. Multilevel Decoding • Now we can start to design for ALUcontrol signal, which depends on: • Opcode (6-bit) field and Function Code (6-bit) field • Brute Force approach: • Use Opcode and Function Code directly, i.e. finding expressions with 12 variables • Multilevel Decoding approach: • Use some of the input to reduce the cases, then generate the full output • Simplify the design process, reduce the size of the main controller, potentially speedup the circuit

  23. Lecture #12: The Processor: Control 5. Intermediate Signal: ALUop • Basic Idea: • Use Opcode to generate a 2-bit ALUop signal • Represents classification of the instructions: • Use ALUop signal and Function Code field (for R-type instructions) to generate the 4-bit ALUcontrol signal

  24. ALU Lecture #12: The Processor: Control 5. Two-level Implementation Step 1. Generate 2-bit ALUop signal from 6-bit opcode. 6 Control Step 2. Generate ALUcontrol signal from ALUop and optionally 6-bit Funct field. ALUop opcode 31:26 rs 25:21 2 rt 20:16 rd 15:11 shamt 10:6 funct 5:0 00: lw, sw 01: beq 10: add, sub, and, or, slt 4 ALUcontrol 0000: and 0001: or 0010: add 0110: sub 0111: set on less than ALU Control 6

  25. Lecture #12: The Processor: Control 5. Generating ALUcontrol Signal 00 xxxxxx 0010 00 xxxxxx 0010 01 xxxxxx 0110 10 10 0000 0010 10 10 0010 0110 10 10 0100 0000 10 10 0101 0001 10 10 1010 0111 Generation of 2-bit ALUop signal will be discussed later 

  26. Lecture #12: The Processor: Control 5. Design of ALU Control Unit (1/2) ALUcontrol3 = 0 • Input: 6-bit Funct field and 2-bit ALUop • Output: 4-bit ALUcontrol • Find the simplified expressions ALUcontrol2 = ? ALUop0 + ALUop1 F1 0 0 X X X X X X 0 0 1 0 0 0 X X X X X X 0 0 1 0 X X X X X X X X X X X X X X X X 0 1 X X X X X X 0 1 1 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 1 0 1 1 0 

  27. ALUop ALUcontrol2 = ALUOp0 + ALUOp1∙F1 ALU Control block ALUOp0 (LSB) ALUcontrol3 ALUOp1 (MSB) 0 ALUcontrol2 F3 ALUcontrol ALUcontrol1 F2 F(5-0) F1 ALUcontrol0 F0 Lecture #12: The Processor: Control 5. Design of ALU Control Unit (2/2) • Simple combinational logic 2

  28. Lecture #12: The Processor: Control 5. Finale: Control Design • We have now considered all individual signals and their expected values • Ready to design the controller itself • Typical digital design steps: • Fill in truth table • Input:Opcode • Output: Various control signals as discussed • Derive simplified expression for each signal

  29. Datapath & Control Lecture #12: The Processor: Control Instruction Memory PC MUX Add 4 Instruction Left Shift 2-bit Address PCSrc Control Branch Inst [31:26] Add Inst [25:21] 5 RR1 RD1 5 is0? MemWrite Inst [20:16] RR2 opcode 31:26 rs 25:21 rt 20:16 rd 15:11 shamt 10:6 funct 5:0 Registers ALU ALUSrc 5 WR ALU result MUX Address MUX RD2 Data Memory MemToReg WD Inst [15:11] 4 Read Data ALUcontrol MUX RegWrite RegDst Write Data Sign Extend Inst [15:0] MemRead Inst [5:0] ALUop ALU Control

  30. Lecture #12: The Processor: Control 5. Control Design: Outputs X X 1 0 0 1 0 1 X 1 X 0 0 0 1 1 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 1 0 0 0 

  31. Lecture #12: The Processor: Control 5. Control Design: Inputs • With the input (opcode) and output (control signals), let’s design the circuit 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 1 0 0 1 1 0 0 23 2B 0 4

  32. Lecture #12: The Processor: Control 5. Combinational Circuit Implementation Opcode Control Signals

  33. Lecture #12: The Processor: Control 5. Combinational Circuit Implementation Opcode Control Signals

  34. Clock Period Clock Read Compute Write Don’t want to read a storage element when it is being written. Lecture #12: The Processor: Control 6. Big Picture: Instruction Execution • Instruction Execution = • Read contents of one or more storage elements (register/memory) • Perform computation through some combinational logic • Write results to one or more storage elements (register/memory) • All these performed within a clock period

  35. Lecture #12: The Processor: Control 6. Single Cycle Implementation: Shortcoming • Calculate cycle time assuming negligible delays: memory (2ns), ALU/adders (2ns), register file access (1ns) • All instructions take as much time as the slowest one (i.e., load) •  Long cycle time for each instruction

  36. Lecture #12: The Processor: Control 6. Solution #1: Multicycle Implementation • Break up the instructions into execution steps: • Instruction fetch • Instruction decode and register read • ALU operation • Memory read/write • Register write • Each execution step takes one clock cycle  Cycle time is much shorter, i.e., clock frequency is much higher • Instructions take variable number of clock cycles to complete execution • Not covered in class: • See Section 5.5 of COD if interested

  37. Lecture #12: The Processor: Control 6. Solution #2: Pipelining • Break up the instructions into execution steps one per clock cycle • Allow different instructions to be in different execution steps simultaneously • Covered in a later lecture

  38. Lecture #12: The Processor: Control Summary • A very simple implementation of MIPS datapath and control for a subset of its instructions • Concepts: • An instruction executes in a single clock cycle • Read storage elements, compute, write to storage elements • Datapath is shared among different instructions types using MUXs and control signals • Control signals are generated from the machine language encoding of instructions

  39. Lecture #12: The Processor: Control Reading • The Processor: Datapath and Control • COD Chapter 5 Sections 5.4 (3rd edition) • COD Chapter 4 Sections 4.4 (4th edition) • Exploration: • ALU design and implementation: • 4th edition (MIPS): Appendix C • http://cs.nyu.edu/courses/fall11/CSCI-UA.0436-001/class-notes.html

  40. Lecture #12: The Processor: Control End of File

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