Concurrent Silicon/Package Design Flow and Chip I/O Planning, an Introduction

1. Concurrent Silicon/Package Design Flow and Chip I/O Planning, an Introduction Bill Acito Cadence Design Systems September 2002

2. Overview • What is concurrent design? • What factors are driving Si-Pkg co-design? • The transition from sequential to parallel environments • What functionality is required for Si-Pkg co-design?

3. Drivers • More functionality, higher performance • More I/O’s: Finding a physical routing solution • Tighter geometries drive increased sensitivity to signal integrity effects • 35nm Node Estimates: • 10000 Balls • 10-20 GHz IC Clock • 4 GHz PCB Clock • 200W heat, 310A

4. IC Continuous ConvergenceThe wire-centric methodology in IC Full-chip virtual prototype “Traditional IC implementation approaches are linear… RTL, gates, power planning, placement, clock tree design, routing… when gates dominate delay this process is predictable. As the percentage of delay in the wires increases, linear flows become more unpredictable and inefficient. Using floor planning… designers can iterate at the placement level to try to find a feasible solution… design teams must use methodologies that generate wires as soon as possible… Strategies that are not clearly focused on rapid wire creation, optimization, and analysis are destined to fail. …continuous convergence [to silicon closure].” “Down to the Wire – Requirements for Nanometer Design Implementation” Ping Chao and Lavi Lev, EEDesign.com Wires the first day and every day Manufacturability Performance Silicon closure

5. …likewise, Si-Pkg-Brd Convergence • The ability to design the chip, the package, and the surrounding system concurrently becomes a significant advantage, if not an enabler • To optimize this concurrent strategy, a single interactive database is essential • Allowing design teams to perform high speed interconnect analysis, both physical and electrical, across the entire system. • Identify where there are “degrees of freedom”, and maximize them

6. Design Flows • Classic • Silicon Driven • Board or Package Driven • Pure Co-design

7. Classic Design Flow • The IC design is handed off to the packaging team – with very little, if any, interaction • Groups are in separate locations, buildings, companies • Speak different languages, view the world differently Package Design IC Design

8. Classic Design Flow Packaging Teams have been left to solve routing and assignment issues. …and yet, packaging costs may soon dominate the total cost of both low- and high-end ICs.

9. Silicon Driven Flow • A flow from the IC designers perspective • Derived from the Classic Design • Needs to determine target die size, I/O Floor Plan, I/O Buffer requirements • Must be done with some understanding of the package, and it’s impact on performance • Die size – impacted by constraints imposed by the available package selections, power and ground rings, wire lengths (in wirebond designs) • I/O matrix -- keys off of feasibility analysis, complexity of escape pattern, routing layers, valid and routable I/O assignment, --- then electrical feasibility and differential pair opportunities

10. Board or Package Driven Flow • PCB assignment may be fixed: replacement part, upgrade part, physical constraints imposed by difficulties in escape routing very large BGAs • I/O placement may be driven by interconnect feasibility • I/O placement driven by a fixed timing budget coming up from the board, other electrical constraints, component placement, or signal performance requirements

11. Full Co-design • Opening up the “solution space” • Identifying and maximizing the degrees of freedom Pkg/Brd Design IC Design

12. Opening Up the Solution Space Package Design Space Package Design Space IC Design Space Board Design Space I/O Placement RDL Routing Die Pad Assignment Ball assignment Board Routing Wiring solution from bump to ball

13. Degrees of Freedom Identify: What is fixed. What has yet to be defined. What can be changed. What must be updated through the design when something is changed.

14. “Pure” Co-design The best possible scenario: • During the product concept phase, the design starts with an estimated number of I/Os and performance requirements • Initial floor planning sets the die size • Power and ground net requirements, wirebond patterns or flip chip escape routing • Information is fed to the formal IC design phase, as well to the package (with an initial template) and board design teams very early in the process • A first order electrical analysis of the entire system can then be performed, from I/O buffer to package ball • Exchange information with SP&R and Packaging design tools and cycle until design closure

15. Key Learnings so far… • Wires, wires, wires • Start with a good assignment • View the entire solution space • Identify the degrees of freedom, maximize what you can change

16. What is needed Imbedded 2D/3D field solvers and topology editor Chip/Package in co-design environment I/O floor planning in the context of the package Communication protocols, common database Power delivery analysis and assignment Constraint management Si – Pkg - PCB

17. Co-Design UI • Simultaneous display and editing of Silicon and Package • Intuitive to both IC and package engineers • Terminology • Visual • Flow driven methodology that promotes “Correct by Design”

18. I/O Assignment • I/O assignment based on package considerations • Hierarchical I/O patterns • I/O Buffer to BGA pad Interconnect Modeling • Constraint Definition • Pattern libraries • Imbedded power consumption requirements

19. I/O Planning for Wire Bond Designs • Bondability based I/O assignment • Power/Ground ring definition • Full interconnect modeling • I/O buffer, Wires, Traces, Vias and Balls • Rules driven package template creation

20. I/O Planning for Flip Chip Designs • I/O assignment based on package considerations • Hierarchical Flip Chip I/O patterns • Die pad, I/O buffer and Escape Pattern • Repeatable “known good” assignments • Redistribution interconnect • Interconnect Modeling • Constraint Definition

21. Route Feasibility Analysis • Routing algorithm-based package ball assignment • Flip Chip escape patterns • Diff pair labeling • Silicon level redistribution: I/O buffer to die pad

22. Signal Integrity Analysis • Full Interconnect Modeling • Power delivery analysis • Evaluating design tradeoffs • Solution space analysis • 2D and 3D field solvers

23. Benefits of Co-Design • Silicon/Package co-design will ensure physical compatibility between the siliconand IC package, reduce or even eliminate re-spins • Power delivery analysis capability for both core and external Pwr/Gnd • Reduced die size with optimized I/O buffer placement and size • Performing upfront SI analysis will allow for package optimization to meet silicon performance targets • Full interconnect modeling, I/O buffer to I/O buffer, and system level constraint definition

24. Less is Better • Less time to market: • Co-design will allow for parallel design and fabrication of both silicon and package • Optimized I/O cell placement reduces time lost for re-spins • Assures package meets design requirements and avoid retooling which can take upwards of 6 – 8 weeks • Cost reduction: • Package optimization rather than package over design. • Reduce number of package layers by optimizing top level silicon for route re-distribution • Avoid cost of silicon re-spins (est. $500K each time)

25. Cadence Chip I/O Planner • Delivers on Cadence’s Design Convergence Strategy: Silicon-Package-Board • Jointly developed with Agere (Announced March 2001) • Full featured physical design environment including route feasibility and redistribution routing, I/O placement optimization, and LEF/DEF support • Integrated high speed SI analysis capability that will enable system level analysis, exercise design tradeoffs and constraint definition • Developed to drop into an existing First Encounter/SOC Encounter flow (intended for the IC designer) • Currently in Beta Program