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## Compactors

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**Generators and**Generators and compactors Compactors**Embedded stimuli**Embedded stimuli generators generators**Test pattern generator is BIST**COMPA C T O R T E S T G E N E R A T O R scan chains Control**Generators**• Capable of generating “good” pseudorandom test patterns • Long aperiodic sequences • No structural dependencies • Low linear dependencies • Capable of driving large number of scan chains • Very simple hardware, small area • Fast operational speed • Easy to synthesize and analyze**Linear feedback shift registers**0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 • A series connection of delay elements (D flip-flops) • All feedback provided by means of XOR gates • The characteristic polynomial: x16 + x10 + x7 + x4 + 1 • Two implementations Larger fanout but smaller delay**Primitive polynomial**1 0 0 0 An n-bit LFSR with nonzero seed generates m-sequence (maximum length sequence) with period 2n-1 1 3 7 15 14 13 10 5 11 6 12 9 2 4 8 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 Generation Testing Generation Testing Checking Absolute Primes**Properties of m-sequence**1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 Shifted by 2 bits 0 1 0 1 0 1 1 0 1 1 0 1 0 0 1 0 0 1 1 1 1 1 0 1 0 0 1 1 0 0 Shifted by 8 bits • It consists of 2n-1 1s and (2n-1 - 1) 0s • There is one pattern of n consecutive 1s and one pattern of n - 1 consecutive 0s • Any pair comprising an m-sequence and its circularly shifted version is identical in 2n-1 - 1 positions and differ in 2n-1 positions • A sum of an m-sequence and its circularly shifted version is another shifted version of that m-sequence**Linear dependencies**d c b a ! 1 0 1 0 1 1 0 0 a d a c d a b c d b c d a b c b d Cannot generate test 111 ! a c a b d c d b c a b 0 1 1 0 Only these 4 combinations are possible d c b a**Probability of linear dependency**- 1 k n i - 2 2 Õ = - p ( n , k ) 1 n - - 2 i 1 = 0 i • Gaussian elimination can be used to determine linear dependencies • Probability of k-bit linear dependency in m-sequence generated by an n-bit LFSR with primitive polynomial • For smaller sequences the probability may be much higher • Trinomials are particularly sensitive**Probability of linear dependency**2n - 1 n ... LFSR k n = 30**Selection of polynomial**• Degree: • Large enough so the states will not repeat • Large enough to reduce linear dependencies • Type • Primitive • Avoid trinomials (increased linear dependencies) • Use at least pentanomials or septanomials • Seed value • Selected through fault simulation • Selected intelligently through reseeding**Two-dimensional generators**11 10 9 8 7 6 5 4 3 2 1 0 Structural dependencies ...**Two-dimensional generators**11 P H A S E S H I F T E R 10 9 8 7 6 5 4 3 2 1 0 Find XOR network which guarantees minimum channel separation**XOR taps selection**! • Determine a dual LFSR • Initialize it to 10 ... 0 pattern • Run it for 2n - 1 - k cycles • Read the resulting content of the dual LFSR Locations of 1s point out positions that should be included in a phase shifter to obtain a sequence shifted by k bits**Application of LFSR duality**Shift 5 6 7 8 9 10 11 12 13 1 0 0 1 1 1 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 1 0 0 1 0 1 1 0 1 1 1 1 0 0 1 1 0 0 0 0 0 0 Dual 1**PRPG with phase shifter**11 10 9 8 7 6 5 4 3 2 1 0 ...**Impact on linear dependency**theoretical limit theoretical limit scan size separation With PS 16-bit type I LFRS 13 polynomials 15 specified bits scan: 16 50 No PS**Extra fault coverage**max avg. min 54 polynomials, 16-, 24- and 32-bit type I LFRSs 0 the lowest fault coverage recorded With phase shifters No phase shifter**Capable of generating m-sequences with primitive polynomials**Improved modularity (compared to LFSRs) Reduced need for phase shifters May exhibit some structural dependencies Cellular automata 0 0 1 1 1 0 1 0 1 0**LFSRs**Internal feedback LFSR External feedback LFSR - many levels of logic - big fan-out**Hybrid LFSR and cellular automaton**Hybrid LFSR Cellular automaton - large gate count - delay and fan-out**Ring architecture**4 8 12 17 20 23 28 1+ x4+ x8+ x12+ x17+ x20+ x23+ x28+ x32 • One sources per one destination • Fast • Modular PRPG**Synthesis**(32-12)/2=10 10+12=22 (32-14)/2= 9 9+14=23 (32-27)/2= 2 2+27=29 9 2 10 23 29 22 1 + x12+ x14 + x27 + x32 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31**Comparison summary**EF LFSR IF LFSR H LFSR CA Ring Fan-out 2 2 k + 1 (2, k +1) 3 2 Levels of logic log2k 1 (1, log2k) 2 1 XOR gates k k k k (k +1) / 2 (k +1) / 2D 2n - 2 k Modularity * k k * (k +1) / 2 * ** *** h(x)= x n + x i + ... + x j + 1 k D only for some polynomials**Reseeding of LFSRs**Final fault grading of the test vectors obtained from the seeds by fault simulation of decompressed patterns Identification of random pattern resistant faults by fault simulation of pseudo-random patterns 4 1 Computation of seeds by solving systems of linear equations through Gaussian elimination Generation of test cubes for random pattern resistant faults using ATPG with dynamic compression, targeting several faults and leaving many “don’t care” inputs 3 2 LFSR Scan chain Seed Test cube**Weighted random patterns**11 10 9 8 7 6 5 4 3 2 1 0 The average number of patterns to detect s-a-0: Pseudo-random: 1/0.5-9 = 512 Weighted PS: 1/(1 - 2-7)-9 1.07**Test response**Test response compactors compactors**Placement of compactor**COMPA C T O R T E S T G E N E R A T O R scan chains**Requirements for Logic BIST**Objective: reduce the volume of test data and still be able to determine if the response was correct Properties of ideal compactors: • simple hardware and small area • tested as part of the embedded test circuitry • simple software • compute the signature at the speed of the test • perform logarithmic compaction of data • no aliasing No scheme meets all criteria, but some come close!**Requirements for deterministic test**• Dramatically reduce volume of output test data • Maintain high test quality • Minimize impact on design and flow • Provide in-production diagnosis**Motivation**Quality >100x X > 1 - D e c o m p r e s s o r 99.99% X 99.99% Diagnosis X tolerance**Quality**Quality D e c o m p r e s s o r 99.99% 99.99%**Compaction**>100x > 1 - D e c o m p r e s s o r**X tolerance**X D e c o m p r e s s o r X X tolerance**Motivation**D e c o m p r e s s o r Diagnosis**Compaction schemes**• Time compactors • polynomial division - signature analysis • arithmetic accumulation • various forms of counting • Space compactors • XOR trees • Finite memory compactors • Convolutional compactors • Block-based compactors**Error models and aliasing**OK 0 Fault detected 1 0 1 2 10 11 3 4 5 6 7 8 9 • Single-bit and burst errors • Equally likely errors • Stationary and non-stationary independent errors • Asymmetric errors Aliasing or error masking - signature obtained from a faulty circuit is the same as that of the fault-free circuit**LFSR and Markov model**0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 1 1 0 1 1 0 0 0 1 1 1 010 010 100 100 100 101 110 110 000 000 000 001 001 001 111 011 011**Transient**0.5 p = 0.1 p = 0.2 p = 0.8 0.4 h(x) = x3 + x2 + 1 p = 0.9 (primitive polynomial) 0.3 Aliasing probability 0.2 0.1 0 10 20 30 40 50 Number of patterns**Aliasing probability**2-n • How likely is it that a fault will generate a signature identical to a fault-free signature? • The Markov chain representing the compaction performed by n-bit LFSR is irreducible, aperiodic, and its transition matrix is doubly stochastic. Thus the probability that it enters any state is provided that a steady state has been reached. For n = 20, p 10-6 and n = 30, p 10-9**Multiple Input Signature Register**• Parallel data acquisition from multiple scan chains • Multiple error injections • High compaction speed • Simple hardware 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0**Time compactors**MISR – infinite memory compactor • Compaction ratios 108 x • Unable to handle unknown states • Multiple-pass complicated fault diagnosis**Space compactors**XOR tree • Smaller compaction than time compactors • Handling of unknown states**Space compactors**• Certain minimum number of outputs required • Improved diagnostic capabilities**Space compactors**Balanced tree is preferable scan chains**Fault cancellation**scan scan**Unknown states**scan X scan X**Selective space compactors**scan scan scan scan • Deterministic compaction control ... ... decoder control**Convolutional compactor 10:1**Polynomials 3/6**Architecture of convolutional compactor**... Injector network ...