Software Vision To Provide Designers The Advantages of….

1. Software VisionTo Provide Designers The Advantages of…. • Methodologies that increase designer productivity • Focus on HDL flows • Delivering the industry’s fastest clock rates • Support for the industry’s biggest devices • Commitment to industry standards (EDIF, VHDL, Verilog) • Complete, ready to use design solutions

2. Advanced Implementation TechnologyUtilized in Alliance & Foundation product families • Performance Based Compilation • Maximizes Clock Rates • Fastest compile times for timing driven designs • Automatic push button design flows • Intuitive graphical user interfaces • Powerful tools require very little interaction • Complete flows for HDL and schematic designs • Auto-interactive control • For even greater performance

3. Innovative Technology Xilinx features not provided by Altera • Design Manager • Save previous versions and revisions automatically • Support for timing between clocks • Allows for more than one clock in a design • Multi-cycle clocks • Avoid over constraining designs • Clock skew • Only Xilinx factors in clock skew when determining clock period • Turns Engine • Achieve up to 25% more performance using workstations on a network • Same constraints for timing analysis & place/route • Don’t have to specify timing requirements twice • Can easily find timing violations

4. XC4000XL Technology: FASTER By Design MHz Min CLOCK SPEED RUNTIME (34% faster) 70 (16% higher) 60 60 64 MHz (average) 50 50 55 MHz (average) 40 40 41 Min (average) 30 30 27 Min (average) 20 20 10 10 0 0 XILINX ALTERA XILINX ALTERA New Xilinx FPGA Implementation Technology Software provides higher system clock speeds and reduced runtimes as compared to Altera MAX+Plus II V8.3 & FLEX10K Design Test Suite (VHDL & Verilog) of actual customer designs ranging from 10K to 100K system gates. (XC4000XL-08)

5. Alliance Series Roadmap A1.4 (Shipping!) A1.5 (Shipping!) A2.1 (Early 1999) • Improved Implementation Run-Times (up to 6X) • Improved Quality of Results • New 4KXV, Spartan, 5K, 3K device support • Functional Simulation Models (UNISIM) • Up to 4X runtime improvements • Constraints Editor • Floorplanner • New Virtex, 9KXL, 4KXLA, SpartanXL device support • Official Support for • MTI • Synplicity • Exemplar • Synopsys XSI Design Guide. • Up to 2X runtime improvements • CPLD Floorplanner • Next generation high volume architecture • Modular Design • Offical Support for • LMG Smartmodels • Quad Motive Timing Analysis

6. Foundation Series Roadmap F1.4 (Shipping!) F1.5 (Shipping!) F2.1 (Q2 1999) • Foundation Express FCS • Improved synthesis technology, flows, QOR • Verilog Support • Improved Implementation Run-Times (up to 6X) • Improved Quality of Results • New 4KXV, Spartan, 5K, 3K device support • Embedded FPGA Express • Unified Project Mgmt. • HDL Simulation ‘Plug-Ins’ • Up to 4X runtime improvements • Constraints Editor • Floorplanner • New Virtex, 9KXL, 4KXLA, SpartanXL device support • HDL Centric Design Entry & Project Management • Improved Simulator Capacity & Performance • Single Push-Button Flows • Improved Error Navigation • Up to 2X runtime improvements • CPLD Floorplanner • Next generation high volume architecture

7. 1.5 Software EnhancementsDirectly address customer needs • New Device Support • 3 FPGA: Virtex, 4KXLA, Spartan XL (XC40110XV, XC40150XV, XC40200XV, XC40250XV) • 1 CPLD: 9500XL • Ease of Use Improvements • Timespecs and Reports • Minimum Delays • Graphical Constraints Editor

8. Graphical Constraint Entry • Guides user to the best constraint methodology • Eliminates need for user knowledge of syntax • Reduces need for user knowledge of nets and components of the design

9. 1.5 Software EnhancementsFaster Runtimes and Higher Performance • Continued Runtime Reductions • Focus on “sweet spot” density • 2-3X faster runtime in place and route • More efficient timing for large designs • Much faster design translation • Up to 8X for large, flat designs • Up to 2X for many small input files • Extend Maximum Device Performance • Fastest Device Speeds • Easier to achieve 50 to 100Mhz • Production Floorplanner

10. Graphical Floorplanner • Add knowledge of the designs structure to increase performance up to 40% • Area constraints for modulesprovide • faster runtimes • higher performance • design changes made easier

11. 1.5 SoftwareMore Customer Driven Enhancements • Minimum delay reporting • For simulation and static timing analysis • XC4000XL family is supported in 1.5 • Other families to roll out as characterization is compete • Automatic pin locking • Automatically generate constraints to lock pins to a specific design revision

12. Future DirectionResponding to the Changing Landscape Evolution of FPGA Design Cores, HDL, Design reuse, Behavioral compiler Larger design teams Schematic Single designer Synthesis Single designer Synthesis and Cores Small team TIMELINE Timing Driven PAR HDL Back Annotation Tighter ties with synthesis vendors Module Compile Module Guide Evolution of FPGA Tools

13. Modular DesignXilinx is Leading the Way • Facilitates Group Design & Reuse • Seamless Integration Between Modules • Extension to leading cores solution • Modular Time Specs • With industry’s best timing constraint language • Modular Incremental Compile • Extensive R&D investment Designer1 Module Designer2 Module Design Reuse Designer3 Module Reduces Compile Time & Increases Performance

14. Modular Design Roadmap • Multiple Design Team Support • Team Oriented Design Management • Module Timing Independence • Auto Timing Budgets • Auto Linking of Modules • Modular Timing Constraints • ECO • Single Module Flow Features • Links to RTL Floorplanning • 1 million+ gate capability • Increased Performance • Reduced Runtime • Modular Guide 1998 1999 2000 2001 2002

15. Modular Design in Version 2.1 • Floorplanning • Detailed and modular physical layout • Interface to 3rd party RTL floorplanners • Implementation • Place and route optimized for modular area constraints • Critical timing path optimization within modules • Much faster runtime for large designs • Guided iterations for synthesis designs • Only changed modules have to be re-placed and routed • Reduces runtime and verification time for unchanged modules

16. Compile Time Leadership 50 40 Up to 3X faster than 1.4 30 Minutes* 20 10 0 2002 2001 1998 1999 2000 * 100k System gate designs (400MHz Pentium) And with ... 1999 Goal: 1 Million Gates in under 1.5 hours! Faster CPUs Faster Compile Times Modular Compile

17. Rapid Time-to-Market Through Guided Designing • Preserve timing • Reduced Runtime • Reduced verificationtime • Guided Synthesis • Modular design methodology • Modular Guided Implementation Existing Design Placed & Routed New Design with Moderate Changes Guided Synthesis • Only re-synthesize new module • Retain most of changed module • Re-optimize new portions Modular Guided Implementation • Only re-compile new module • Retain most of changed module • Place & Route new portions

18. Reduce Your Time-to-MarketUsing Cores • Significant time and risk reduction by using pre-verified Cores • Reduced compile time Design from scratch Learn Design Implement Verify Reference design, generic core L D I V Complete Core solution L D I V Months

19. Summary Gates: 1,500,000 Freq.: 150 MHz+ Xilinx programmable Software Solutions for… • The best in design performance • The best in timing driven runtimes • The best HDL design flow support • The industry’s most advanced technology • Best positioned to deliver the future Gates: 1,000,000 Freq.: 100 MHz+ Gates: 85K Freq.: 65MHz+ 2000 1997 1998 1999