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AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

AVID: Breaking Processors for Increased Performance & Reduced Power Consumption. Douglas Lacy & Daniel LeCheminant CS 252 December 10, 2003. Background. Todd Austin’s DIVA paper DIVA dynamically verifies all instructions, guarding against transient and permanent faults

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AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

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  1. AVID: Breaking Processors for Increased Performance & Reduced Power Consumption Douglas Lacy & Daniel LeCheminant CS 252 December 10, 2003

  2. Background • Todd Austin’s DIVA paper • DIVA dynamically verifies all instructions, guarding against transient and permanent faults • Austin speculated that DIVA could allow throttling of processor clock speed AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

  3. Background / Motivation • DIVA: maintains correctness even with malfunctioning hardware • Is there a way to “break” the core processor in such a way as to optimize it? • Remove rarely-used components? • Reduce tolerance in clock cycle, voltage, etc? • May be possible to dynamically alter processor to be only as correct as necessary AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

  4. Motivation • Some components of processors exist to ensure correctness in rarer cases • May waste resources and cycles to check these cases • With DIVA, we can ignore them, mostly • “Rare” is variable • Could be lazy with some computations, need to be more strict with others • Which are possible is dependent on program AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

  5. Motivation AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

  6. Motivation • Specifically, what can we remove/throttle? • Memory disambiguation • Branch prediction • Branch checking • Exceptions • Long-latency operations (multiply & divide) • Rare instructions? • Prefetching AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

  7. Proposal: AVID • AVID: Architecture that Varies, Input Dependent • Use a DIVA unit to provide verification, and also feedback to the core processor • Can dynamically throttle operations from most time/power-consuming and correct to least consuming and sometimes incorrect • Won’t require much more hardware than standard DIVA AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

  8. AVID! AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

  9. More AVID • Branch predictors • Static, bimodal, 2-level, hybrid • Multiply/Divide • Truncate inputs, run for fewer cycles • Loads • Allow them to proceed past unresolved stores • Clock cycle throttling • Start fast, reduce speed if errors crop up AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

  10. Methodology • Simulate in SimpleScalar • Base architecture: Standard DIVA • Modify simple scalar to include a core & DIVA unit • Modify base architecture into AVID • DIVA catches all errors so processor is still functional & reliable AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

  11. Comparison • Run benchmarks on both architectures & compare performance (SPEC or similar) • CPI: Read from simulator output • Exec. Time: Total cycles * cycle time • Power Consumption • Total cycles * constant + branch predictions * constant for type of pred. • Amount of hardware AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

  12. Results: CPI in Best Case SimpleScalar run with relaxed constraints without producing errors AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

  13. Results: Power Consumption AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

  14. Conclusions • No long benchmarks successfully run • Preliminary results promising in some areas, discouraging in others • AVID may be best for reducing power consumption • AVID could be extended for further dynamic alteration of processors, limited reconfigurable computing AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

  15. Future Work • Extension of AVID to throttle other possible components • Further static removal of components • Actual full SPEC benchmark comparisons of standard, DIVA, and AVID architectures • Exploration of speculation in several ways, using AVID for verification and feedback AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

  16. Questions? • You know you have them! Ask! • Go on, pick us apart! AVID: Breaking Processors for Increased Performance & Reduced Power Consumption

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