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eFEX Functionality Overview

eFEX Functionality Overview. Introduction Input Data & Bandwidth Algorithms RT Output Data & Bandwidth Readout Data & Bandwidth Latency Conclusion. Introduction. This is a preliminary review of a prototype module Many details of eFEX requirements are still to be fixed Algorithms

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eFEX Functionality Overview

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  1. eFEX Functionality Overview Introduction Input Data & Bandwidth Algorithms RT Output Data & Bandwidth Readout Data & Bandwidth LatencyConclusion Ian Brawn

  2. Introduction • This is a preliminary review of a prototype module • Many details of eFEX requirements are still to be fixed • Algorithms • Data formats • Bandwidth • Prototype will help us fix these • Algorithms and data formats given here are intended to be indicative examples • Metric against which resources of eFEX can be measured • Intention here is not to show that all eFEX details are fully defined, but that eFEX hardware is capable of performing (& testing) operations foreseen Ian Brawn

  3. L1Calo Upgrade, Run 3 (Phase-I), Initially… L1Calo e/,  TOBs ECAL (digital) L1Topo L1CTP Electron Feature Extractor L1A supercells Optical Plant Hub ROD 6.4 Gb/s Jets, , ETETmiss Jet Feature Extractor To DAQ Hub ROD RoI Jets, ETETmiss Jet Energy Processor CMX To DAQ 0.1 0.1(,) ECAL (analogue) Pre-processor To RODs nMCM e/,  HCAL (analogue) ClusterProcessor CMX 0.1 0.1(,) To RODs To RODs Ian Brawn

  4. L1Calo Upgrade, Run 3 (Phase-I), …Later L1Calo e/,  TOBs ECAL (digital) L1Topo L1CTP Electron Feature Extractor L1A supercells Optical Plant Hub ROD 6.4 Gb/s Jets, , ETETmiss Jet Feature Extractor To DAQ Hub ROD RoI Jet Energy Processor To DAQ 0.1 0.1(,) ECAL (analogue) Pre-processor nMCM HCAL (analogue) To RODs Ian Brawn

  5. L1Calo Upgrade, Run 4 (Phase-II) L1 L0Calo e/,  TOBs ECAL (digital) L0Topo L0CTP L1Muon L1Topo L1CTP Electron Feature Extractor L0A L1A supercells Optical Plant Hub ROD HCAL (digital) 6.4 Gb/s Jets, , ETETmiss L1Calo Jet Feature Extractor To DAQ Hub ROD RoI L1Track To DAQ R3 Ian Brawn

  6. eFEX Block Diagram eFEX Module 4  Processor FPGAs e/ extractor MTP Op Rx Fan out De-serialiser Serialiser Op Tx 448 1212 144 Results Merger 36 312 From Optic Plant To L1Topo extractor Control FPGA To/from Hub IPbus Rolling Memory LAPP Card Derandomiser IPMC Readout Interface FPGA To ROD on Hub Configuration Controller FPGA L1A (L0A) TTC Interface From TTC interface on Hub Ian Brawn

  7. Input Data & Bandwidth • ECAL & HCAL signals: • Line rate = 6.4 Gb/s baseline • (Prototypes →9.6 Gb/s, 12.8 Gb/s) • 8B/10B (DC balance & clock recovery) • 10-bit cyclic redundancy check • ECAL fibre: • 1-4-4-1 samples in depth for tower of 0.1  0.1 (  ) • BCMUX Neighbouring towers in  • 2 towers / fibre • ~10-bit data/sample ~120 bits of 128 / BC • HCAL fibre: • Towers of 0.1  0.1 (  ) summed in depth • 8 towers / fibre • ~10-bit data/tower  ~90 bits of 128 / BC • If links > 6.4 Gb/s successful, best use of bandwidth to be evaluated re physics • BCMUX? • Increase window size? • Increase dynamic range? Samples from ECAL for 0.1  0.1 (   ): Ian Brawn

  8. Algorithms (1) • Purpose: identify e/ and (non-large)  candidates • Algorithms • Seed • R:identify local maxima in 2nd sampling region • E(2)0.0750.2/ E(2)0.1750.2> threshold • 3—4 reduction in trigger rate cf. current trigger • Measure energy • Weighted sum in eta, phi and depth • Hadronic vetos, e.g. • f3: • E(3)0.20.2/ E(1,2)0.0750.2 + E(3)0.20.2 < threshold • Hadcore • E(HCAL)0.20.2< threshold • If all algorithms passed, Trigger Object generated Ian Brawn

  9. Algorithms (2) • Details of algorithms to be defined, complexity will be comparable to algorithms shown • Processor FPGA = XC7V550T • e/ algorithm for 0.5 x 0.8 (  ) core occupies ~4% of internal resources • Window size is crucial parameter • Bottleneck at FPGA input • Overlapping windows → Fan out • Baseline algorithm window is 0.3 x 0.3(   ) • Sufficient for e/ • For , 0.5 x 0.5 (,  ) slightly better • Layout of spare inputs defined in spec. allows adoption at higher link speeds 3 towers of 0.1 in  5 towers of 0.1 in  Ian Brawn

  10. TOB format Ian Brawn

  11. eFEX RT Output & Merging 56 signals (112 tracks) @ 320 Mb/s  448 b/BC • Real-time output to L1Topo • ≤ 4 L1Topo modules  2 L1Topo FPGAs • 2 fibres → each of ≤ 8 L1Topo FPGAs • Same data transmitted to each FPGA • For TOBs ~30 bits, 8b/10b, 2 fibres: • Core area of 1.6  0.8 (  ) • 6.4 Gb/s  ~ ≤ 8 TOBs/BC • 9.6 Gb/s  ~ ≤ 12 TOBs/BC • 11.2 Gb/s  ~ ≤ 14 TOBs/BC • Simulation required to confirm • TOB size • No. TOBs that need to be processed • But also allow bandwidth upgrade path • ≤ 4 fibres → each of ≤ 8 L1Topo FPGAs • Dual-star on eFEX to avoid bottleneck • 2 fibres for , 2 for e/ • Round up to 36 fibres/module 448 pins 224 pins 2 fibres @ 11.2 Gb/s = 448 b/BC FPGA A FPGA B  8 spare FPGA D FPGA C  8 FPGA pins: Merging IO: 448 Readout IO: 32 Control & Spare: 120 -------------------------------- 600 Ian Brawn

  12. Readout Input Logic Feature Finding Merging Real-Time Logic Scrolling RAM … … … L1A L1A L1A FIFO … … … Readout Logic Packet Building Readout Data MGTs Ian Brawn

  13. Draft Readout Data Format • Only 1 Format of readout packet • ROD re-formats as necessary for DAQ, L2, & (Phase-2) L1 • Data read out: • TOBs • Input Data • Readout optional • Pre-scaled by programmable deadtime • Limit to 1/10 trigger rate • Expanded TOBs • Readout optional Ian Brawn

  14. XTOB Format • (Optionally) sent to Readout path in addition to RT TOBs • 64 bits • More energy bits, isolation variables rather than threshold flags, (redundant) machine information • Diagnostic use Ian Brawn

  15. Readout Bandwidth L0A rate at Phase-2 • Assumes all possible data transmitted • Input data, all channels, but pre-scaled to 1/10 of trigger rate • XTOBs: max no. TOBs found by eFEX (160) • Copy of RT output (TOBs): 2 fibres @ 6.4 Gb/s • Result ≤ 6.4 Gb/s per link to ROD (just) • Higher RT link speeds would require higher readout link speeds • But, this is unrealistic worst -case estimate • Need better estimate of TOB numbers Ian Brawn

  16. Latency • Current estimate of total latency is 13.5 BC • From input of eFEX to input of L1Topo • < half latency arises from algorithmic processing • Large contribution from (de-)serialisation and (de-)MUX necessary for high-speed data transfer • To refine estimate require • Prototype implementations of algorithms • Format of serial data Ian Brawn

  17. Conclusion • Many fine details of eFEX requirements still to be defined • Algorithms, no. TOBs to be handled, Dynamic range of inputs & outputs, data formats…. • Dependant on physics: simulation programme will address • In parallel hardware prototype will enable investigation of bandwidth, signal integrity, module control, cooling…. • We believe we understand requirements well enough that prototype specified is capable of performing role foreseen for final eFEX Ian Brawn

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