Designing of a D Flip-Flop Final Project ECE 491

1 / 13

# Designing of a D Flip-Flop Final Project ECE 491 - PowerPoint PPT Presentation

Designing of a D Flip-Flop Final Project ECE 491. Objectives. To familiarize with the function of the D flip- flop and it's operation. To Draw the schematic and the layout with clocked input Perform DRC check and generate LVS To do the simulation and observed the output waveforms

I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.

## PowerPoint Slideshow about 'Designing of a D Flip-Flop Final Project ECE 491' - harrison-lopez

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.

- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

### Designing of a D Flip-FlopFinal ProjectECE 491

Objectives
• To familiarize with the function of the D flip- flop and it's operation.
• To Draw the schematic and the layout with clocked input
• Perform DRC check and generate LVS
• To do the simulation and observed the output waveforms
• To Vary the output load(1pf to 5pf) and observed outputs
D Flip Flop (Specification)
• A signal input and a clock signal is used
• AMI-0.6micron process is used
• Wp=7.5 u, Wn= 3.0 u, Ln=Lp=0.6u
• Pre and Post-layout simulations using spectra
• Rise time, Fall time and propagation delay increase for the loading effects
Why DFF
• Preferred type for integrated circuit applications (DFF)
• S-R flip flop has indeterminate state when both inputs are high
• The JKFF simplifies the RSFF truth table but keeps two inputs.
Symbol

CLK

Q

DFF

D

QB

Schematics

Q

QB

Inverter

Nor

And

And

Nor

INVERTER

NAND

NOR

AND