designing of a d flip flop final project ece 491 n.
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Designing of a D Flip-Flop Final Project ECE 491. Objectives. To familiarize with the function of the D flip- flop and it's operation. To Draw the schematic and the layout with clocked input Perform DRC check and generate LVS To do the simulation and observed the output waveforms

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objectives
Objectives
  • To familiarize with the function of the D flip- flop and it's operation.
  • To Draw the schematic and the layout with clocked input
  • Perform DRC check and generate LVS
  • To do the simulation and observed the output waveforms
  • To Vary the output load(1pf to 5pf) and observed outputs
d flip flop specification
D Flip Flop (Specification)
  • A signal input and a clock signal is used
  • AMI-0.6micron process is used
  • Wp=7.5 u, Wn= 3.0 u, Ln=Lp=0.6u
  • Pre and Post-layout simulations using spectra
  • Rise time, Fall time and propagation delay increase for the loading effects
why dff
Why DFF
  • Preferred type for integrated circuit applications (DFF)
  • S-R flip flop has indeterminate state when both inputs are high
  • The JKFF simplifies the RSFF truth table but keeps two inputs.
symbol
Symbol

CLK

Q

DFF

D

QB

schematics
Schematics

Q

QB

Inverter

Nor

And

And

Nor

slide8

INVERTER

NAND

NOR

AND