저전력 통신 SoC 설계

1. 저전력 통신 SoC 설계 조 준 동 VADA Lab. SungKyunKwan University 2006.8

2. 발표순서 • 저전력 SoC 설계 기초 • Power metric • 기본적인 저전력 설계 기술 • 재구성구조를 이용한 저전력 설계 • Reconfigurable Radio Systems (Software Defined Radio) • 병렬처리를 통한 저전력 설계 • Network-centric Design • Reliable Design • Deep submicron Clock and Power 관리 기법

3. 저전력 설계 기초

4. 이동 단말기 = 소형+저전력+기능 GPS Noise cancellationheadphones Cochlear implant Cellular phone Medicalwatch Hearing aid Portable audio Digital still camera Digital radio

5. 미래의 모바일 컴퓨팅 • 실시간 처리 이동 슈퍼 컴퓨팅 • Speech recognition, Cryptography. • Augmented reality. • 16개의 Pentium-4 필요 • 2004 Intel P4 @3GHz; 55M TR’s 122mm2 0.09u • 2014 20GHz 0.03u • 저전력을 만족하면서 고성능 • requires (massive) parallelism • Multi-processor systems • Subsystem integration Mudge et al:

6. Emb. Systems Prog. 2005: # of Processors per chip

7. Processor Heterogeneity

8. Parallelism favors lower power solutions P. G. Paulin et al, “Parallel Programming Models for a Multiprocessor SoC Platform Applied to Networking and Multimedia”, IEEE Transactions on VLSI Systems, Vol. 14, No. 7, July 2006

9. Parallelism Inside the Processor Chris Rowen, President and CEO, Tensilica, Inc.

10. Multiple concurrent processorsmuch lower energy Chris Rowen, President and CEO, Tensilica, Inc.

11. Keys to Efficient MPFlexible range of topologies Chris Rowen, President and CEO, Tensilica, Inc.

12. Two Multi-processor Design Flows Chris Rowen, President and CEO, Tensilica, Inc.

13. Anatomy of a Cellular Phone

14. Why is SDR Challenging? Scott Mahlke

15. Core Technologies for Future Networks –OFDM 64 –2048 point FFT –MIMO –use of multiple antennas for transmission/reception –Low density parity check codes •Key insight: SDR requires innovation across algorithm, software and hardware •SDR platforms offer low-cost, longevity, and adaptability

16. Parallel Architectures

17. 저전력 디바이스의 필요성 • 실용적 (Reducing power requirements of high throughput portable applications) • 경제적 (Reducing packaging costs and achieving memory savings) • 기술적 (Excessive heat prevents the realization of high density chips and limits their functionalities)

18. VDD PMOS Network iDD Vin + Vo CL - NMOS Network 동적 전력 소모 Dynamic Power • Average power consumption by a node cycling at each period T: • Average power consumed by a node with partial activity • (only a fraction  of the periods has a transition)

19. 정적 전력 소모 Static power Pstatic = VCC x Ntr X Ileak 0

20. SCALING TREND • Keeping the pace with Gene’s Law: DPS Chip’s energy efficiency (MIPS/Watt) doubles every 18 Month • Low Cost • High flexibility • Reduce idle power in idle state • Gene’s Law  Tech&Circ: Voltage islands, Arch: MPSoC • Low Cost  Integrate, but only when cost effective • Push towards A & D integration • High flexibility  Software radios, reconfigurable architectures • Reduce static power in idle state  Variable Vdd, VT

21. NOC NOC MPSoC IO IO IO COPR COPR SOCBUS MEM MEM CPU MEM MEM Vdd1 Vdd3 Vdd2 • From single-master CPU to MPSoC • From bus-based interconnect to NoC • Emphasize reuse, flexibility A distributed system on a single chip!

22. 저전력 소모 기술 개발 현황

23. 에너지 감축을 위한 2가지 요소 • C0 • redundant h/w extraction • Locality of reference • Demand-driven / Data-driven computation • Preservation of data correlations • Power down techniques (Clock gating, dynamic power management) • All in one Approach (SOC) • Vdd • Dynamic voltage scaling based on workload • 2-D pipelining (systolic arrays) • Parallel processing

24. Parallel-Pipelined Architectures Ppar=0.2Pref

25. Loop unrolling

26. 루프 풀기에 의한 저전력 기법 Loop Unrolling for Low Power

27. 대수 변화 및 상수 전달에 의한 방법

28. Loop Unrolling for Low Power

29. 수체계 변환에 의한 저전력 FFT • Logarithmic Number System의 사용 • Log 수 체계 • look-up table • 크기 영역에 대해서 2의 log를 취한 값을 산출한다. • 변환된 log 값을 어떤 n 비트로 제한된 표현 범위의 값을 갖는 2진수로 표현. • LNS 연산 • 곱셈 : 가산 • 가감산 : look-up table • 연산의 정확도 • 소수부가 2비트 이상의 경우 BER 성능 감소 없음 • 전력 소모 • 실험 결과 일반 butterfly FFT에 비하여 약 60% 정도 까지 전력 소모가 감소함 • 7.8mW -> 3.1mW

30. 분할을 통한 적절한 전압 공급 SLOW 3V FAST 5V SLOW SLOW 3V 3V SLOW 3V

31. Using Vdd programmabilityWayne Burleson • High Vdd to devices on critical path • Low Vdd to devices on non-critical paths • Vdd Off for inactive paths A – Baseline Fabric B – Fabric with Vdd Configurable Interconnect This work builds on a similar idea for FPGAs described in: Fei Li, Yan Lin and Lei He. Vdd Programmability to Reduce FPGA Interconnect Power, IEEE/ACM International Conference on Computer-Aided Design, Nov. 2004

32. DIGLOG 곱셈기 1st Iter 2nd Iter 3rd Iter Worst-case error -25% -6% -1.6% Prob. of Error<1% 10% 70% 99.8% With an 8 by 8 multiplier, the exact result can be obtained at a maximum of seven iteration steps (worst case)

33. 재구성구조를 이용한 저전력 설계

34. Task 1 Task N W A B X C Y D E Z A A B B H H I I J J W W Y Y D D C C E E D X X C Z Z E Reconfigurable Hardware 재구성을 이용한 에너지 효율증대 Doing More by Doing Less • 알고리즘 진화에 따른 유연성 • 다양한 표준 수용 • Dynamic QoS 제공 • 전력 감축 • 설계 비용 감축: • 개발 및 유지 보수해야 하는 플랫폼 감소 • 임베디드 프로세스 사용

35. Radio systems:Different power Constraints 10 W 802.11a 802.11bg 3G 1 W 100 mW Bluetooth UWB ZigBee 10 mW ZigBee UWB 1 mW 0 GHz 1GHz 2 GHz 3 GHz 4 GHz 5 GHz 6 GHz

36. Technology Evolution

37. SDR = Reconfigurable Radios

38. SDR Configuration • Modulation Format • QPSK • DQPSK • p/4 DQPSK • {16,64,256,1024} QAM • OFDM • OFDM CDMA • Digital Down/Up Conversion (DDC) • Channel Center • Decimation/Interpolation rates • Compensation Filters • Matched Filter a = {0.25,0.35,...} Soft Radio Digital Signal Processing Engine • Channel Access • CDMA • TDMA • FEC • Convolutional • Reed-Solomon • Concatenated Coding • Turbo CC/PC • (De-)Interleave • DSSS • Rake, track, acquire • Multi User Detect. (MUD) • ICU • Network Interface Definition • Security • Beam Forming

39. 재구성 HW/SW 구조

40. 재구성 DSP를 이용한 사례: DMB 변복조부