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Enhancing Performance in Superscalar Processors with the EASE Branch Predictor

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The EASE Branch Predictor, developed by Serene Banerjee, Lizy K. John, and Brian L. Evans, addresses the challenges faced by superscalar processors with multiple pipeline stages and high instruction issue rates. This predictor effectively increases performance by accurately predicting branch occurrences and addresses, which reduces missed speculations and enhances throughput. Approaches include global history tracking, counter-based, correlation-based, and hybrid predictors. Research shows EASE outperforms traditional predictors in common benchmarks like SPEC95, with significant improvements in prediction accuracy.

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Enhancing Performance in Superscalar Processors with the EASE Branch Predictor

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  1. The EASE Branch Predictor Serene Banerjee, Lizy K. John, Brian L. Evans The EASE Branch Predictor December 16th, 2000

  2. Motivation • Superscalar processor • 10-12 pipeline stages • 64-way issue • Instructions repeat • Increase performance • Predict branch occurrence • Predict branch address • Missed speculations decrease throughput The EASE Branch Predictor

  3. Branch address ... x x x x x x x x ... ... ... ... Global history Others Branch Predictors Counter-based Correlation-based XOR Prediction G-share Hybrid ... The EASE Branch Predictor

  4. Branch Predictors • Counter-based [Madeswaran, Mathialagan, 1990] • Table of counters indexed with instruction address • One-level predictor • Correlation-based[Yeh, Patt, 1991] • Table of counters indexed with instruction address and global counter storing branch prediction history • Two-level predictor • G-share [McFarling, 1993] • XOR address and history to randomize prediction The EASE Branch Predictor

  5. Hybrid Predictors • Cascaded predictor [Driesen, Holzle; 1998] • Filter rule: Add new entry if first stage is incorrect • Predict rule: Use second stage if there is no table miss • Performance-dependent switching [Patil, Emer; 1999] Branch target First stage Filter Predict Branch address Prediction Second stage The EASE Branch Predictor

  6. Branch Predictor Results • 100 instructions program: one-level is better • 10,000 instructions program: G-share is better The EASE Branch Predictor

  7. EASE Predictor • G-share has more cold start misses than one-level • Embed smaller one-level predictor into G-share • Switch permanently to G-share after certain time The EASE Branch Predictor

  8. Branch address ... x x x x x x x x ... ... ... ... Global history EASE Predictor One level G-share XOR Prediction Counter The EASE Branch Predictor

  9. Simulations • Shade http://www.simplescalar.org [Austin, Burger, 1997] • Tracer for SPARC applications • SPEC 95 benchmarks • Gcc, Go, Compress, Ijpeg, Li, M88ksim, Perl • Measuring prediction accuracy • Predict branch outcome and branch target address • If branch is predicted taken and actually taken, prediction is correct if branch target buffer matches • If predicted not taken and actually not taken, prediction is correct The EASE Branch Predictor

  10. Results • EASE has comparable prediction results for SPEC95 benchmarks to a hybrid predictor • EASE outperforms hybrid predictors for gcc The EASE Branch Predictor

  11. Conclusions • More efficient VLSI implementation for EASE • Has fewer counters than one-level predictor • Needs no decision circuit as does hybrid predictor • Outperforms hybrid and cascaded predictor for gcc benchmark: 8% vs.10-14% misprediction • Comparable results for SPEC95 benchmarks • Prevalent predictors: 1 - 14% misprediction • EASE predictor: 2 - 18% misprediction http://www.ece.utexas.edu/~serene/software/ease The EASE Branch Predictor

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