GLAST Large Area Telescope: Electronics, Data Acquisition & Flight Software System Engineering

1. Gamma-ray Large Area Space Telescope GLAST Large Area Telescope: Electronics, Data Acquisition & Flight Software System Engineering Gunther Haller Stanford Linear Accelerator Center Manager, Electronics, DAQ & FSW LAT Chief Electronics Engineer haller@slac.stanford.edu (650) 926-4257

2. System Engineering Outline • System Overview • Changes since PDR • External Interfaces • Internal Interfaces • Technical Budget • Verification & Test • Risk • FMEA • Reliability Allocations • Parts and Spares Plan • Drawing Tree

3. Data-Acquisition (DAQ) System Overview • Configuration, triggering, event-flow control and readout, monitoring, and supply of power to • 16 Calorimeter and Tracker towers with a total of 850,000 tracker channels and 3,000 calorimeter channels • 12 ACD front-ends with a total of 208 ACD channels • Interface to spacecraft for control, data, monitoring, and power • Trigger system (hardware selection of possibly interesting events) • Event filtering • Housekeeping • Operational thermal control

4. Tower Electronics Module Interface to calorimeter and tracker on each tower Monitoring Combination of sub-system trigger signals to primitives Event buffering GAS Unit Command-response unit receives and distributes command, clock, and data Global trigger unit generates LAT-wide readout decision signals based on trigger primitives from TEM’s and ACD Event-builder unit builds complete LAT events out of asynchronous event-fragments; Forward complete events to dynamically selected target EPU’s or spacecraft ACD electronics module tasks much like TEM for TKR/CAL EPU: Event processor unit runs filter algorithm to reduce 10kHz input event rate down to 30 Hz (with two EPU’s) SIU: Spacecraft interface unit controls LAT and interfaces to spacecraft Instrument software runs on EPU and SIU processors only Power system not shown LAT Electronics Hierarchy

5. LAT Electronics Physical TKR Front-End Electronics (MCM) 16 Tower Electronics Modules • DAQ electronics module (DAQ-EM) • Power-supplies for tower electronics ACD Front-End Electronics (FREE) TKR CAL Front-End Electronics (AFEE) CAL Global-Trigger/ACD-EM/Signal-Distribution Unit* 3 Event-Processor Units (2+1 spare) • Event processing CPU • LAT Communication Board • SIB Spacecraft Interface Unit • Spacecraft Interface Board (SIB): Spacecraft interface for MIL1553 control & data • LAT control CPU • LAT Communication Board (LCB): LAT command and data interface Power-Distribution Unit (PDU)* • Spacecraft interface, power • LAT power distribution • LAT health monitoring * Primary & Secondary Units shown in one chassis

6. Changes since PDR • Spacecraft Selection and Meetings: • PDU was moved to opposite side of SIU to match SC power/C&DH physical partitioning • Signal levels (discretes, 1 PPS, Science Interface, GBM GRB signal) were officially changed to LVDS (before undefined or RS422), March 03 • Recently finalized power, analog monitoring, and discrete interface to SC • Defined MIL1553 command set/interface • Separated SIU prime and redundant into separate (and identical) crate assemblies since cross-connection to SC prime and redundant was solved on the SC-LAT interface level and lead to removal of direct SIU-SIU inter-connections Before SC selection After SC selection

7. Changes since PDR (Con’t) • Event-Builder was moved from CPU crates to GAS unit • Reduced complexity of inter-connections • Reduced hardware from 3 event-builder blocks to 2 (1 prime, 1 redundant), and power dissipation from two event-builder blocks to one • SIU crate was modified to be the same as EPU crate • Removes mechanical, thermal, electrical design effort for one assembly • Moved SC science interface from Spacecraft Interface Board in SIU to event-builder in GASU • Additional benefit that SIB board is almost identical to existing SECCI version (both boards are designed by NRL/Silver Engineering), major simplification • Science interface on GASU is small change since GASU already transmits event data to LAT CPU’s, so additional target is incremental • Added SIB board in each EPU crate to provide local EEPROM • Simplification in software effort. • No remote booting code development/testing required.

8. External Interfaces • All external DAQ interfaces released with the exception of spacecraft interface and mechanical/thermal interface (mainly to X-LAT plate)

9. Internal Interfaces • All internal interfaces are final, documents are being updated, release before CDR

10. DAQ Technical Budget Summary Technical Resources • DAQ Mass • Sub-system allocation: 220 kg • Detailed estimate: 199.3 kg • DAQ Power • Subsystem allocation: 318 W • Detailed estimate: 313.8 W • CPU Cycles • Allocation: 2 CPU’s • Detailed estimate: < 1 CPU • For detailed breakdown see Power/Mechanical/Software presentations

11. Verification & Test Model Development • Hardware and software development closely integrated • Design of hardware versus software complexity optimized continuously • Software runs with LAT engineering model electronics • Continuous hardware versus software verification • Full system including sub-system electronics from and at other institutions • Independent verification process • Exchange of hardware and software -> • ACD hardware, TKR hardware, CAL hardware • DAQ hardware • Flight software, I&T software • ACD Scripts, TKR scripts, CAL scripts, DAQ scripts • No integration at flight- LAT integration stage of components which have not operating fully integrated in earlier stages • Exception is spacecraft, since simulator is only simulating and is not real hardware/software Hardware Design Fab Test Software Design/Develop Develop/Test Formal Test Release to I&T

12. Verification & Test (Con’t) Development Cycles EM 1 Release to I&T Release to sub-systems EM2 Release to I&T Release to sub-systems FU Release to I&T • Three development cycles • Engineering Model 1 • Single tower, single CPU • Engineering Model 2 • Multiple tower, single CPU • Flight Model • Multiple towers, multiple CPU’s • Peer-Reviews after end of each development cycle • In addition regular LAT reviews (Manufacturing Readiness Review, etc)

13. Verification Matrix (Doors Example Page)

14. Test Matrix Applies to each board and assembly. In this slide the tests at each level are listed

15. Electrical & Environmental Test Flow LAT Qual • LAT Test Accept • LAT Test TEM DAQ/PS Qual • Elec Accept • Elec PDU EPU SIU GASU TEM DAQ TEM PS Qual • Elec • Sine Vibe • Random Vibe • Thermal Vac • EMI/EMC Accept • Elec • Static Load • Random Vibe • Thermal Vac Qual • Elec • Sine Vibe • Random Vibe • Thermal Vac • EMI/EMC Accept • Elec • Static Load • Random Vibe • Thermal Vac Qual • Elec • Sine Vibe • Random Vibe • Thermal Vac • EMI/EMC Accept • Elec • Static Load • Random Vibe • Thermal Vac

16. Risk • No single DAQ system failure can degrade LAT Electronics capabilities below minimum science requirements • Failure in SIU, PDU, or GASU can require use of the respective redundant unit • Failure in one of the two EPU’s can require use of the redundant EPU unit. A second failure will reduce the available EPU CPU power by a factor of 2. • Failure in TEM power-supply or TEM DAQ module can lead to • Loss of a full tower (most of the assembly is single string) • Loss of the calorimeter or parts of it • Loss of the tracker or parts of it

17. Electronics Risk Summary

18. Electronics Risk Summary

19. FMEA Fault Tree Analysis – LAT-TD-01757-01 (Draft) FTA’s completed on EPU’s, GASU’s, PDU’s, SIU’s, TEM’s, & TEM/PS’s No single point failures without ground contingency – (Software) Most components multiply redundant (More than one redundant component) Non-redundant with in redundant systems identified. Failure Mode & Effects Analysis - LAT-TD-00374-01 (Being Drafted) Failure modes identified Effects analysis underway Probability being linked to component failure No criticality 1, or 2 failures Few 2R failures, mostly 2MR thru 5 failures

20. Reliability Allocation Mission 70% (Pf = .3) Observatory 85% (Pf = .15) LAT 85% (Pf = .15) DAQ 96% (Pf = .04) Tower Electronics GASU PDU SIU EPU Harness TEM DAQ TEM PS SIB LCB PSB CPU incl FSW Back Plane

21. Parts Lists • Parts Lists • Electrical component list for DAQ submitted to Electrical Parts Control Board and most parts are approved (see later presentation) • Mechanical components list for DAQ submitted to Mechanical Parts Control Board

22. Spares Plan * Qualification Models are flight spares ** EPU does not have separate qualification since crate is the same as SIU crate

23. Technical Issues and Status • No known technical issues in respect to functionality and performance except potentially • TEM GTCC and GCCC ASIC (back from fabrication end of 3/03) • Reliability; Analysis in progress

24. Drawing Tree (Example)

25. Summary • Changes since PDR described • Interfaces documents released and under change control • Technical budget at CDR level with sufficient margin • Verification and test plans documented • Risks contained in LAT database with mitigations • FMEA and reliability well under way • Drawing tree well advanced • System engineering will be at CDR level by CDR time • Main remaining item is completion of reliability analysis