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Chapter 10 Input/Output Interface Circuits and LSI Peripheral Devices. 1. Core and special-purpose I/O interface 2. Byte-wide output ports using isolated I/O 3. Byte-wide input ports using isolated I/O 4. Input/output handshaking and a parallel printer interface

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Chapter 10 Input/Output Interface Circuits and LSI Peripheral Devices


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    1. Chapter 10 Input/Output Interface Circuits and LSI Peripheral Devices • 1. Core and special-purpose I/O interface • 2. Byte-wide output ports using isolated I/O • 3. Byte-wide input ports using isolated I/O • 4. Input/output handshaking and a parallel printer interface • 5. 82C55A programmable peripheral interface • 6. 82C55A implementation of parallel input/output ports • 7. Memory-mapped input/output ports

    2. Chapter 10 Input/Output Interface Circuits and LSI Peripheral Devices • 8. 82C54 programmable interval timer • 9. 82C37 programmable direct memory access controller • 10. Serial communication interface • 11. Programmable communication interface controller • 12. Keyboard and display interface • 13. 8279 programmable keyboard/display controller

    3. Fig.10-1 Sixty-four-line parallel output circuit A15L=1

    4. Figure 10.1 Sixty-four-line parallel output circuit for 8088 microcomputer

    5. 微算機概論 • 2.期末報告:0%~10%(加分) 2010/01/07 (星期四)繳交 題目與微算機概論相關

    6. Chapter 10 Homework • 3, 5, 7, 9, 13, 15, 17, 19, 21, 23, 25, 27, • 29, 31, 33, 35 • 39, 43, 45, 47, 50, 55, 59, 61, 65, 67, 69

    7. Fig. 10.1 output address

    8. Output the byte contents of the memory address

    9. Output the byte contents of the memory address

    10. Figure 10.2 Driving an LED

    11. Figure 10.3 Sixty-four-line parallel input circuit

    12. I/O address of part 7

    13. Input the byte contents of input port 7

    14. Reading the setting of a switch

    15. Parallel printer interface

    16. I/O interface and handshaking

    17. Figure 10.6 Handshaking printer interface circuit A15L=1

    18. Ex 10.5 Port address

    19. Ex 10.6 Flowchart

    20. Ex 10.6

    21. 10.5 82C55A Programmable peripheralinterface • 82C55 provides a flexible parallel interfaces, which includes features such as single-bit, and byte-wide input output ports; level-sensitive inputs; latched outputs; strobed input and outputs; strobed bidirectional input/output. These features are selected under software control. • 8-bit bidirectional data bus • Read/write control signals • Register select code • Chip select and reset

    22. Figure 10.7 Block diagram of the 82C55A

    23. Figure 10.8 Addressing an 82C55A using the microprocessor interface 1

    24. Figure 10.9 Control-word bit functions It must be at logic 1(active) Whenever the mode of operation is to be changed

    25. Operation mode • Mode 0 selects what is called simple I/O operation. By simple I/O, we mean that the lines of the port can configured as level-sensitive inputs or latched output. • Fig. 10-11 Control words I/O configurations

    26. Figure 10.10 Mode 0 port pin functions

    27. Ex 10.7 Mode 0 operation Fig. 10-11 (c)

    28. Mode 0 control words and corresponding input/output configuration

    29. Figure 10.11

    30. Figure 10.11

    31. Mode 1 operation • Mode 1 operation represents what is known as strobed I/O. The ports of the 82C55A are put into this mode of operation by setting D7=1 to activate the mode-set flag and setting D6D5=01 and D2=1. • In this way, the A and B ports are configured as two independent byte-wide I/O ports, each of which has a 4-bit control/data port associated with it. The control/data ports are formed from the lower and uppernibbles of port C, respectively. Fig10-12 lists the mode 1 functions of each pin at ports A, B, and C.

    32. Figure 10.12 Mode 1 port pin functions

    33. Figure 10.13 Mode 1, port A input configuration

    34. Figure 10.14 Timing diagram for an input port in mode 1 configuration

    35. Control signals • Strobe input: STB • Input buffer full: IBF • Interrupt request: INTR • Acknowledge: Ack • Interrupt enable: INTE • Output buffer full: OBF

    36. Ex 10.8

    37. Figure 10.15 Mode 1, port B configuration

    38. Mode 2 operation • Mode 2 represents the strobedbidirectional I/O • The key difference is that now the port works as either inputs or outputs and control signals are provided for both functions. Only port A can be configured to work in a 8-bit bidirectional I/O.

    39. Figure 10.16 Mode 2 port pin functions

    40. Figure 10.17 Mode 2 input/output configuration

    41. Figure 10.18 Bit set/reset format Ex 10.9

    42. Ex 10.9

    43. Figure 10.19 Combined mode 2 and mode 0

    44. Figure 10.10 Control word in control register

    45. Figure 10.11 Control word in control register

    46. Mode 1 status information • The format of the status information input by reading port C of an 82C55A operating in mode is shown in Fig. 10-20(a). Note that if the ports are configured for input operation, the status byte contains the values of the IBF and INTR outputs and INTE flag for both ports. Once read by the MPU, these bits can be tested with other software to control the flow of the program. • By using a software handshake sequence that tests the bits to change the program sequence, hardware signals such as interrupts can be saved.

    47. Figure 10.20 Mode 1 status information for port C

    48. 10.6 82C55A Implementation of parallel input/output ports • The 82C55A PPI can be used to design a more versatile parallel I/O interfaces. This is because its ports can be configured either as input or outputs under software control. • Address bus  port numbers • Data bus  Port (channel)

    49. Figure 10.21 82C55A parallel I/O ports in an 8088-based microcomputer

    50. Ex 10.12 Port C of PPI 14