Week 3 Presentation

1. Week 3 Presentation Kevin Cheung Michael Glowacki Alex Romine Dave Sexton

2. Opcodes register-register instructions (R-type) OPCODE FUNCT sll = r,0x04 000000 000100 srl = r,0x06 000000 000110 sra = r,0x07 000000 000111 add = r,0x20 000000 100000 addu = r,0x21 000000 100001 sub = r,0x22 000000 100010 subu = r,0x23 000000 100011 and = r,0x24 000000 100100 or = r,0x25 000000 100101 xor = r,0x26 000000 100110 seq = r,0x28 000000 101000 sne = r,0x29 000000 101001 slt = r,0x2a 000000 101010 sgt = r,0x2b 000000 101011 sle = r,0x2c 000000 101100 sge = r,0x2d 000000 101101 movi2s = r,0x30 000000 110000 movs2i = r,0x31 000000 110001 movf = r,0x32 000000 110010 movd = r,0x33 000000 110011 movfp2i = r,0x34 000000 110100 movi2fp = r,0x35 000000 110101 movi2t = r,0x36 000000 110110 movi2i = r,0x37 000000 110111 sltu = r,0x3a 000000 111010 sgtu = r,0x3b 000000 111011 sleu = r,0x3c 000000 111100 sgeu = r,0x3d 000000 111101

3. Opcodes – cont. floating-point instructions (R-type) addf = f,0x00 000001 000000 subf = f,0x01 000001 000001 multf = f,0x02 000001 000010 divf = f,0x03 000001 000011 addd = f,0x04 000001 000100 subd = f,0x05 000001 000101 multd = f,0x06 000001 000110 divd = f,0x07 000001 000111 cvtf2d = f,0x08 000001 001000 cvtf2i = f,0x09 000001 001001 cvtd2f = f,0x0a 000001 001010 cvtd2i = f,0x0b 000001 001011 cvti2f = f,0x0c 000001 001100 cvti2d = f,0x0d 000001 001101 mult = f,0x0e 000001 001110 div = f,0x0f 000001 001111 eqf = f2,0x10 000001 010000 nef = f2,0x11 000001 010001 ltf = f2,0x12 000001 010010 gtf = f2,0x13 000001 010011 lef = f2,0x14 000001 010100 gef = f2,0x15 000001 010101 multu = f,0x16 000001 010110 divu = f,0x17 000001 010111 eqd = f2,0x18 000001 011000 ned = f2,0x19 000001 011001 ltd = f2,0x1a 000001 011010 gtd = f2,0x1b 000001 011011 led = f2,0x1c 000001 011100 ged = f2,0x1d 000001 011101

4. Opcodes – cont. general instruction OPCODE j = j,0x02 J 000010 jal = j,0x03 J 000011 beqz = b,0x04 I 000100 bnez = b,0x05 I 000101 bfpt = b0,0x06 I 000110 bfpf = b0,0x07 I 000111 addi = i,0x08 I 001000 addui = i,0x09 I 001001 subi = i,0x0a I 001010 subui = i,0x0b I 001011 andi = i,0x0c I 001100 ori = i,0x0d I 001101 xori = i,0x0e I 001110 lhi = i1,0x0f I 001111 rfe = n,0x10 J 010000 trap = t,0x11 J 010001 jr = jr,0x12 I 010010 jalr = jr,0x13 I 010011 slli = i,0x14 I 010100 nop = n,0x15 R 010101 srli = i,0x16 I 010110 srai = i,0x17 I 010111 seqi = i,0x18 I 011000 OPCODE snei = i,0x19 I 011001 n/a slti = i,0x1a I 011010 n/a sgti = i,0x1b I 011011 n/a slei = i,0x1c I 011100 n/a sgei = i,0x1d I 011101 n/a lb = l,0x20 I 100000 n/a lh = l,0x21 I 100001 n/a lw = l,0x23 I 100011 n/a lbu = l,0x24 I 100100 n/a lhu = l,0x25 I 100101 n/a lf = l,0x26 I 100110 n/a ld = l,0x27 I 100111 n/a sb = s,0x28 I 101000 n/a sh = s,0x29 I 101001 n/a sw = s,0x2b I 101011 n/a sf = s,0x2e I 101110 n/a sd = s,0x2f I 101111 n/a sltui = s,0x3a I 111010 n/a sgtui = s,0x3b I 111011 n/a sleui = s,0x3c I 111100 n/a sgeui = s,0x3d I 111101 n/a

5. Zero Extender

6. Zero Extender - Trace

7. SRL Shifter

8. SRL Shifter - Trace

9. SRA Shifter

10. SRA Shifter - Trace

11. Register File

12. Register File – Trace

13. 1 Bit ALU – Implemented XOR

14. 1 Bit ALU Trace

15. 32 Bit ALU

16. 32 Bit ALU - Trace

18. Plan Layout of Processor

19. Control Signals • Implement a PLA that interprets the opcode of the DLX processor. • Need to decide what control signals we will need and what they will be for each instruction.

20. Hazards • Data • Detection: Test if destination register of previous instructions are the same as the source register of the current instruction. • Handling: Forward the data from the previous instruction.

21. Hazards • Structural • Detection: Happens if 2 registers would need to write a register at the same time. • Handling: Insert a stall

22. Hazards • Control • Detection: Any conditional branch • Handling: Stall the pipeline until the branch result is known.