PADI status. PADI. FEE1. Mircea Ciobanu 11 th CBM Collaboration Meeting February 26-29, 2007, GSI. Outline. Status of the PADI: - electrical measured parameters - results in the beam test for rate evaluation - preparations for beam test of t What to do next Summary and Outlook.
11th CBM Collaboration Meeting
February 26-29, 2007, GSI
- electrical measured parameters
- results in the beam test for rate evaluation
- preparations for beam test of t
Measurement phase of PADI
beam the rate capability and the stability of the system in real conditions.
PADI test PCBThe PADI together with aSC Diamond (4 pixels) detector
of counts :
pixel #1 6.22030 x106
pixel #26.24211 x106
pixel #4 6.22465 x106
average: 6.22902 x106
individual error ~ +/- 0.2%
September 25 - 28, 2007 Dresden
The PADI design was successful tested, all channels are operational.
The connection of PADI with our TAQUILA3 Data Acquisition system
The first results indicate:
Time res.(@10mV) [ps] < 10
Gain ~ 60
Bandwidth [MHz] ~ 180
Linear range [mV] ~ -5 to 5
CTRR [dB] ~ 26 - 40
CMRR [dB] > 40
Input impedance  ~ 48 - 58
Power [mW/Ch] ~ 31
The PADI design was successful tested, together with a 4 pixels SC diamond detector. The system was stable in under beam conditions.
The AC transmission measurements shows a possible instability of the PADI preamplifier cell.
The connection of PADI with the detector is critical: the line used should have a flat frequency characteristic of the impedance to avoid particularly resonances.
If the input signal is near the threshold limit, the discriminated output signal has a very low width (~1ns). We have tried to transport such signals through a 110 twisted pair LAN-K5 cable and the channel rate limit was 1.5 x 108 hits/s.
Technological details for the direct bonding of the PADI ASIC on the pcb. In the FOPI new START system we will test two variants: in air bond-wires with mechanical protection and Glob Top (epoxi compound) protection.
We started from the NINO1-CERN ASIC schematics used for the ALICE ToF. For a simple comparison between time over threshold and Q measurement for WALK correction, we have added an supplementary buffer block to obtain both information's: time and energy. The whole design was matched for CMOS 0.18 m technology.
Very high time resolution
Cope with pads and strips RPC's
Lower Power consumption
Lower price per channel
1. Four channels instead of three.
2. The increase of closed loop stability.
3. The increase of bandwidth of the preamplifier cell.
The redesign work can be finished at the end of May and the layout at the end of July.
September 20-22, 2006 Strasbourg
t ~√Nd /(As*√BW)
- Special simulations of the system stability to be above the suspicious of instability.
- The increase of PADI preamplifier - discriminator actual bandwidth is a hard task, but we will try to evaluate the limit of the used architecture. We will focus on the reduction of the parasitic capacitances present at the preamplifier input and output ports which in this moment dominates.
Research Infrastructure Activity under the FP6
"Structuring the European Research Area" programme (HadronPhysics, contract number RII3-CT-2004-506078).