audio subword sorter unit on merger for secure transmission

1. Audio Sub word Sorter Unit on Merger SorterNetwork For Secure Transmission Mr. Gaurav Bansod Mtech (Embedded Systems) Symbiosis Institute Of Technology

2. AIM • Low power applications is major area of concern. • Software cryptography in audio as well as video applications. • Hardware implementation of software permutation algorithm are proved to be more efficient. Gaurav Bansod

3. AIM • GRP algorithms most attractive in terms of sorting and cryptographic contents. • Low power HDL based design • Enhanced Merger Sorter Network(EMSN) • Modified Enhanced Merger Sorter (MEMS) • Paper proposes a new structure REMS(Re modified Enhanced merger sorter Network) which is rich in encryption standards and consumes less power. Gaurav Bansod

4. ENCRYPTION • Security Reasons. • Latest revelations tells about software algorithm can be decoded. • Advanced trend started as Hardware Implementation of Software Algorithms. • Results in rich Encryption standards, Lesser power if implemented as ‘ASIC’. Gaurav Bansod

5. ALGORITHM • Let Pi represent the i(th) MIS in P. (x, y) denotes the operations that combine integer sequence x and y into a longer sequence. Sort(x) is a function that sorts elements in sequence x in increasing order. P can be represented by k MISes as follows: • P = (P1, P2, P3,…, Pm, Pm+1 , Pm+2…,Pk-1, Pk) • Note that m = k/2 , and P1, P2, P3, …, Pm is the first half MISes. Gaurav Bansod

6. ALGORITHM 1. Generate temporary sequences T1, T2,…,Tm: For i = 1, 2,… ,m-1 • Ti = (Pi , Pi+m) • If (k is odd) then Tm = Pm else • Tm=(Pm , Pk) 2. Generate Q: • For i = 1, 2,… , m • Qi= Sort(Ti) Gaurav Bansod

7. ALGORITHM CONT… • Let Q = (Q1, Q2,Q3,…,Qm). 3. Generate control bits c: • Q can also be considered as a bit string: • Q = (Q1, Q2, Q3,…,Qm) = (b0, b1, b2, …,bn-1) For j = 0, 1,… , n-1 • if (bj is in P1, P2, P3,… , or Pm) • cj = 0 else • cj = 1 Gaurav Bansod

8. CODE WORD GENERATION Gaurav Bansod

9. LOGIC Gaurav Bansod

10. BASIC IDEA • Control Words are generated according to GRP algorithm • Main aim is to Concentrate 1’s on Left Hand side • (A7,A3),(A6,A2),(A5,A1),(A4,A0) • IST STAGE • EQUIVALENT SWAPPED BITS • A7 A2 A5 A0 A3 A6 A1 A4 Gaurav Bansod

11. Modified Enhanced Merger Sorter Network • GRP algorithm generates Control words and accordingly bits are swapped • MSB’S are preserved • No clear cut implementation of GRP algorithm • A Single Control Word for Structure Gaurav Bansod

12. MEMS Gaurav Bansod

13. MEMS • Care is taken in MEMS that MSB’s should not get shuffled because if MSB’s are lost we won’t reconstruct information • Showing poor encryption and which results in unbounded hierarchy and more power consumption. • Loosing the connection between GRP algorithm and its implementation as Hardware. Gaurav Bansod

14. Re modified Enhanced Merger Sorter • Drawbacks in MEMS removed. • To improve Encryption Standards • Less power. • Clear Representation of GRP algorithm Gaurav Bansod

15. REMS • Different control words for different stages of structure • Rich Encryption Standards • Lesser No of multiplexers. • Preserving essence of Cryptography. Gaurav Bansod

16. REMS STRUCTURE • Encryption for 16 bit – Divided into two 8 bits • Subword Parallelism. • Left Datapath and Right Datapath • Transmitter and Receiver structure is designed Gaurav Bansod

17. REMS LEFTDATAPATH TRANSMITTER Gaurav Bansod

18. SWAPPED BITS • 1st STAGE (A6,A2) AND (A4,A0) EQUIVALENT SWAPPED BITS A7 A2 A5 A0 A3 A6 A1 A4 • 2nd STAGE (A5, A2) AND (A3,A0) EQUIVALENT SWAPPED BITS A7 A2 A6 A0 A4 A5 A1 A3 • 3rd STAGE (A1,A3) EQUIVALENT SWAPPED BITS A7 A2 A6 A0 A1 A5 A4 A3 Gaurav Bansod

19. REMS LEFTDATAPATH RECEIVER Gaurav Bansod

20. Receiver End • 1st STAGE (A2,A6) AND (A0 ,A4) SWAPPED BITS A7 A6 A2 A4 A1 A5 A0 A3 • 2nd STAGE (A6,A2) AND (A3,A1) SWAPPED BITS A7 A6 A5 A4 A0 A2 A1 A3 • 3rd STAGE (A3,A0) SWAPPED CONTROL BITS A7 A6 A5 A4 A3 A2 A1 A0  Gaurav Bansod

21. REMS Rightdatapath • Rich Encryption Standards • Inverted Control bits • Swapped bits should not be swapped again Gaurav Bansod

22. RIGHTDATAPATH Tx and Rx • Similarly rightdatapath stucture is designed according to grp algorithm with inverted control bits • At Rx end data gets decoded with REMS rightdatapath receiver structure Gaurav Bansod

23. RIGHTDATAPATH Tx AND Rx Gaurav Bansod

24. REMS ALGORITHM • Number of Multiplexers are reduced • Better Power Results. • High Encryption standards • HDL implementation Gaurav Bansod

25. Results and Analysis Gaurav Bansod

26. RESULTS Gaurav Bansod

27. DELAY CALCULATION Gaurav Bansod

28. CONCLUSION • GRP instruction is useful not only for fast permutations of n bits, but also for sorting n subwords. This versatility is important if GRP is to be included in a general-purpose processor. • RMSN algorithm provides high encryption standards as compared to previous algorithm . As this algorithm consists of Lesser Muxes ,so it would result in low power as well as low area which would be advantageous for ASIC designing. Since this algorithm is implemented in hardware its speed is also more and can be implemented for Audio as well as video Application. • In this paper algorithm is implemented for 16 bit it can be extended for 32, 64 bit also. This algorithm can be implemented for bubble sort,selection sort effectively . This algorithm is reconfigurable which is new era in ASIC designing Gaurav Bansod

29. CONCLUSION • RMSN algorithm can be implemented by butterfly and ibutterfly structure so that permutations can be done till 64 bits. • This paper is real time application and can be implemented for audio as well as video security applications. • The table above shows area will also get reduced. As mentioned from previous papers EMSN is the fastest solution with a minimum delay. So RMSN is more faster as compared to EMSN, so more lesser delays as shown in paper. Gaurav Bansod

30. FUTURE WORK • Same structure can be implemented for 32 bits and 64 bits . • Comparisons can be done with all Existing algorithms • Can be implemented as “ASIC”: • Pattern selection by user, Gaurav Bansod

31. REFERENCES • Karthigaikumar , K Baskaran, ”Hardware Implementation of Low Power Audio Sub word Sorter Unit for High Security Transmission” International Journal of Computer and Electrical Engineering, Vol. 1, No. 2, June 2009. • GiorgosDimitrakopoulos, Christos Mavrokefalidis, Kostas Galanopoulos and DimitrisNiolos, “Sorter based permutation units for Media-Enhanced Processors” IEEE Transactions on VLSI systems, vol 15, no. 6, pp 711-715, June 2007 • Zhijie Shi, Ruby B. Lee,” Bit Permutation Instructions for Accelerating Software Cryptography”, Application-Specific Systems, Architectures, and Processors, 2000. Proceedings. IEEE International Conference ,JULY 2000 • Jer Min Jou, Yun Lung Lee, Chen Yen Lin and Chien Ming Sun, “A Novel Reconfigurable computation unit for DSP applications”, IEEE comp. society annual symp. on VLSI, ISVLSI’07, pp 439- 444, 9-11 March 2007 • YedidyaHilewitz, Zhijie Jerry Shi and Ruby B. Lee, “Comparing Fast Implementations of Bit Permutation Instructions” Signals, Systems and Computers, 2004. Conference Record of the Thirty-Eighth Asilomar Conference 7-10 NOV 2004 • Zhijie Shi and Ruby B. Lee,” Subword Sorting with Versatile Permutation Instructions” Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD’02) • Ruby B. Lee, Z. J. Shi and Y. L. Yin,Ronald L. Rivest M.J.B. Robshaw” On Permutation Operations in Cipher Design” Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004. International Conference 5-7 April 2004 • Z.J.Shi and R.B.Lee, “Implementation Complexity of bit permutation instructions”, in Proc.Asilomar Conf. Signals Stst. Comput, pp 879-886, 2003. • NavidLashkarian, Ed Hemphi, Helen Tarn, Hemang Parekh and Chris Dick, “Reconfigurable Digital Front End Hardware for wire less base-station transmitters: Analysis, Design and FPGA implementation”, IEEE transactions on circuits and systems, vol 54, No. 8, pp 1666-1677, Aug 2007. Gaurav Bansod

32. THANK YOU Gaurav Bansod